From: Gajanan Bhat <gajanan.bhat@intel.com>
Date: Wed, 28 Mar 2012 20:39:30 +0000 (-0700)
Subject: drm/i915: program drain latency regs on ValleyView
X-Git-Tag: v3.5-rc1~83^2~140^2~38
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=12a3c0551137425a9678d1b9f0495b625550f092;p=pandora-kernel.git

drm/i915: program drain latency regs on ValleyView

This patch adds support for programming drain latency registers of Pondicherry
memory arbiter of Valleyview.

v2: clarify function names (Daniel)
    fix summary typo (Daniel)
v3: add parens (Ben)
    make drain function return bool (Ben)

Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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