From: Ke Wei Date: Fri, 23 May 2008 08:23:22 +0000 (+0200) Subject: [ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR define X-Git-Tag: v2.6.27-rc1~850^2~2^8~25 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1219715de70956557b9dedf3ee021a73d4f4ec52;p=pandora-kernel.git [ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR define Some Feroceon-based SoCs have an MBUS bridge interrupt controller that requires writing a one instead of a zero to clear edge interrupt sources such as timer expiry. This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform. Signed-off-by: Lennert Buytenhek --- Reading git-diff-tree failed