From: Svyatoslav Ryhel <clamor95@gmail.com>
Date: Mon, 24 Mar 2025 19:24:45 +0000 (+0200)
Subject: ARM: tegra: clock: take in account PLLD/D2 enable bit on clock_set_rate
X-Git-Tag: v2025.07-rc1~69^2~22
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0edc47ba7332c72ae1d18003a18c717143cab78b;p=pandora-u-boot.git

ARM: tegra: clock: take in account PLLD/D2 enable bit on clock_set_rate

PLLD and PLLD2 clocks possess a unique enable bit within their
miscellaneous register. Take this into account when using clock_set_rate
function.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index a375693481e..4f0cc19df50 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -703,6 +703,12 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
 	else
 		writel(base_reg, &simple_pll->pll_base);
 
+	/* PLLD and PLLD2 are only clocks which have ENABLE bit */
+	if (clkid == CLOCK_ID_DISPLAY)
+		setbits_le32(&pll->pll_misc, BIT(PLLD_CLKENABLE));
+	if (clkid == CLOCK_ID_DISPLAY2)
+		setbits_le32(&simple_pll->pll_misc, BIT(PLLD_CLKENABLE));
+
 	/*
 	 * Changing clocks was never intended in the U-Boot for Tegra.
 	 * If a clock is changed after clock_init() the parent rate is wrong.