From: Andi Kleen <ak@suse.de>
Date: Sat, 29 Jul 2006 19:42:37 +0000 (+0200)
Subject: [PATCH] x86_64: On Intel systems when CPU has C3 don't use TSC
X-Git-Tag: v2.6.18-rc3~8
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0e5f61b00c577da698fb00cd9c91a96b79044dfd;p=pandora-kernel.git

[PATCH] x86_64: On Intel systems when CPU has C3 don't use TSC

On Intel systems generally the TSC stops in C3 or deeper,
so don't use it there. Follows similar logic on i386.

This should fix problems on Meroms.

Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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