From: Sudhakar Mamillapalli Date: Tue, 10 Apr 2012 21:10:58 +0000 (-0700) Subject: serial/8250_pci: Clear FIFOs for Intel ME Serial Over Lan device on BI X-Git-Tag: v3.5-rc1~146^2~30^2~1 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0ad372b962d109323d18ac2aa118b2ad100eb8dd;p=pandora-kernel.git serial/8250_pci: Clear FIFOs for Intel ME Serial Over Lan device on BI When using Serial Over Lan (SOL) over the virtual serial port in a Intel management engine (ME) device, on device reset the serial FIFOs need to be cleared to keep the FIFO indexes in-sync between the host and the engine. On a reset the serial device assertes BI, so using that as a cue FIFOs are cleared. So for this purpose a new handle_break callback has been added. One other problem is that the serial registers might temporarily go to 0 on reset of this device. So instead of using the IER register read, if 0 returned use the ier value in uart_8250_port. This is hidden under a custom serial_in. Cc: Nhan H Mai Signed-off-by: Sudhakar Mamillapalli Acked-by: Alan Cox Signed-off-by: Dan Williams Signed-off-by: Greg Kroah-Hartman --- Reading git-diff-tree failed