From: Andreas Herrmann <andreas.herrmann3@amd.com>
Date: Thu, 18 Sep 2008 19:12:10 +0000 (+0200)
Subject: x86: c1e_idle: don't mark TSC unstable if CPU has invariant TSC
X-Git-Tag: v2.6.27-rc8~27^2~1
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=09bfeea13cea843fb03eaa96b5d891fa0abdcc90;p=pandora-kernel.git

x86: c1e_idle: don't mark TSC unstable if CPU has invariant TSC

Impact: Functional TSC is marked unstable on AMD family 0x10 and 0x11 CPUs.

This would be wrong because for those CPUs "invariant TSC" means:

   "The TSC counts at the same rate in all P-states, all C states, S0,
   or S1"

(See "Processor BIOS and Kernel Developer's Guides" for those CPUs.)

[ tglx: Changed C1E to AMD C1E in the printks to avoid confusion
	with Intel C1E ]

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---

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