From: Chon Ming Lee <chon.ming.lee@intel.com>
Date: Wed, 9 Apr 2014 10:28:17 +0000 (+0300)
Subject: drm/i915/chv: Trigger phy common lane reset
X-Git-Tag: omap-for-v3.16/fixes-against-rc1~44^2~38^2~150
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=076ed3b2955e5934e137abff39fe9e7180f236fe;p=pandora-kernel.git

drm/i915/chv: Trigger phy common lane reset

During cold boot, the display controller needs to deassert the common
lane reset.  Only do it once during intel_init_dpio for both PHYx2 and
PHYx1.

Besides, assert the common lane reset when disable pll.  This still
to be determined whether need to do it by driver.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
[vsyrjala: Don't disable DPIO PLL when using DSI]
[vsyrjala: Don't call vlv_disable_pll() by accident on CHV]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
[danvet: Move part of a moved comment back as suggested by Imre since
it's valid for both byt and chv.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

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