From: Heikki Krogerus Date: Mon, 17 Jun 2013 10:25:46 +0000 (+0300) Subject: ACPI / LPSS: mask the UART TX completion interrupt X-Git-Tag: omap-for-v3.11/fixes-for-merge-window~19^2~15^2~1 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=06d8641504726322fca54400bbac982bd44f9a27;p=pandora-kernel.git ACPI / LPSS: mask the UART TX completion interrupt Intel LPSS provides an extra TX byte counter and an extra TX completion interrupt for some of its bus controllers. However, there is no use for the extra UART interrupt and it has to be masked out during initialization. Otherwise, if the firmware does not mask the interrupt and the driver does not clear it, it may cause an interrupt flood freezing the board to happen. Add code masking that problematic interrupt to the ACPI LPSS driver. [rjw: Changelog] Signed-off-by: Heikki Krogerus Signed-off-by: Rafael J. Wysocki --- Reading git-diff-tree failed