From: Dmitri Vorobiev Date: Mon, 14 Jan 2008 21:27:46 +0000 (+0300) Subject: [MIPS] Malta: Fix reading the PCI clock frequency on big-endian X-Git-Tag: v2.6.24~27^2~1 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0487de91427925e7c43debeb948bdf53b10ef32c;p=pandora-kernel.git [MIPS] Malta: Fix reading the PCI clock frequency on big-endian The JMPRS register on Malta boards keeps a 32-bit CPU-endian value. The readw() function assumes that the value it reads is a little-endian 16-bit number. Therefore, using readw() to obtain the value of the JMPRS register is a mistake. This error leads to incorrect reading of the PCI clock frequency on big-endian during board start-up. Change readw() to __raw_readl(). This was tested by injecting a call to printk() and verifying that the value of the jmpr variable was consistent with current setting of the JP4 "PCI CLK" jumper. Signed-off-by: Dmitri Vorobiev Signed-off-by: Ralf Baechle --- Reading git-diff-tree failed