From: Markos Chandras <markos.chandras@imgtec.com>
Date: Thu, 30 Jan 2014 17:21:29 +0000 (+0000)
Subject: MIPS: mm: c-r4k: Detect instruction cache aliases
X-Git-Tag: v3.15-rc1~125^2~162
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=02dc6bfb080e8205aacea5c4b4dd6a9bd4c9406e;p=pandora-kernel.git

MIPS: mm: c-r4k: Detect instruction cache aliases

The *Aptiv cores can use the CONF7/IAR bit to detect if the core
has hardware support to remove instruction cache aliasing.

This also defines the CONF7/AR bit in order to avoid using
the '16' magic number.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6499/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

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