From: addy ke Date: Tue, 14 Oct 2014 06:09:21 +0000 (+0800) Subject: i2c: rk3x: adjust the LOW divison based on characteristics of SCL X-Git-Tag: omap-for-v3.19/fixes-rc1~91^2~46 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0285f8f5fd7cf7f458e13d9189eb735dacc244b5;p=pandora-kernel.git i2c: rk3x: adjust the LOW divison based on characteristics of SCL As show in I2C specification: - Standard-mode: the minimum HIGH period of the scl clock is 4.0us the minimum LOW period of the scl clock is 4.7us - Fast-mode: the minimum HIGH period of the scl clock is 0.6us the minimum LOW period of the scl clock is 1.3us I have measured i2c SCL waveforms in fast-mode by oscilloscope on rk3288-pinky board. the LOW period of the scl clock is 1.3us. It is so critical that we must adjust LOW division to increase the LOW period of the scl clock. Thanks Doug for the suggestion about division formulas. Signed-off-by: Addy Ke Tested-by: Heiko Stuebner Reviewed-by: Doug Anderson Reviewed-by: Max Schwarz Signed-off-by: Wolfram Sang --- Reading git-diff-tree failed