--- /dev/null
+From: "Rajendra Nayak" <rnayak@ti.com>\r
+To: <linux-omap@vger.kernel.org>\r
+Subject: [PATCH 01/02] OMAP3 CPUidle driver\r
+Date: Tue, 10 Jun 2008 12:39:00 +0530\r
+\r
+This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver\r
+before it queries the governor for the next state.\r
+\r
+Signed-off-by: Rajendra Nayak <rnayak@ti.com> \r
+\r
+---\r
+ arch/arm/mach-omap2/Makefile | 2 \r
+ arch/arm/mach-omap2/cpuidle34xx.c | 293 ++++++++++++++++++++++++++++++++++++++\r
+ arch/arm/mach-omap2/cpuidle34xx.h | 51 ++++++\r
+ arch/arm/mach-omap2/pm34xx.c | 5 \r
+ drivers/cpuidle/cpuidle.c | 10 +\r
+ 5 files changed, 359 insertions(+), 2 deletions(-)\r
+\r
+Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile\r
+===================================================================\r
+--- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:33.855303920 +0530\r
++++ linux-omap-2.6/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:39.569121361 +0530\r
+@@ -20,7 +20,7 @@ obj-y += pm.o\r
+ obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o\r
+ obj-$(CONFIG_ARCH_OMAP2420) += sleep242x.o\r
+ obj-$(CONFIG_ARCH_OMAP2430) += sleep243x.o\r
+-obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o\r
++obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o\r
+ obj-$(CONFIG_PM_DEBUG) += pm-debug.o\r
+ endif\r
+ \r
+Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c\r
+===================================================================\r
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000\r
++++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c 2008-06-10 11:41:27.644820323 +0530\r
+@@ -0,0 +1,293 @@\r
++/*\r
++ * linux/arch/arm/mach-omap2/cpuidle34xx.c\r
++ *\r
++ * OMAP3 CPU IDLE Routines\r
++ *\r
++ * Copyright (C) 2007-2008 Texas Instruments, Inc.\r
++ * Rajendra Nayak <rnayak@ti.com>\r
++ *\r
++ * Copyright (C) 2007 Texas Instruments, Inc.\r
++ * Karthik Dasu <karthik-dp@ti.com>\r
++ *\r
++ * Copyright (C) 2006 Nokia Corporation\r
++ * Tony Lindgren <tony@atomide.com>\r
++ *\r
++ * Copyright (C) 2005 Texas Instruments, Inc.\r
++ * Richard Woodruff <r-woodruff2@ti.com>\r
++ *\r
++ * This program is free software; you can redistribute it and/or modify\r
++ * it under the terms of the GNU General Public License version 2 as\r
++ * published by the Free Software Foundation.\r
++ */\r
++\r
++#include <linux/cpuidle.h>\r
++#include <asm/arch/pm.h>\r
++#include <asm/arch/prcm.h>\r
++#include <asm/arch/powerdomain.h>\r
++#include <asm/arch/clockdomain.h>\r
++#include <asm/arch/irqs.h>\r
++#include "cpuidle34xx.h"\r
++\r
++#ifdef CONFIG_CPU_IDLE\r
++\r
++struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];\r
++struct omap3_processor_cx current_cx_state;\r
++\r
++static int omap3_idle_bm_check(void)\r
++{\r
++ /* Check for omap3_fclks_active() here once available */\r
++ return 0;\r
++}\r
++\r
++/* omap3_enter_idle - Programs OMAP3 to enter the specified state.\r
++ * returns the total time during which the system was idle.\r
++ */\r
++static int omap3_enter_idle(struct cpuidle_device *dev,\r
++ struct cpuidle_state *state)\r
++{\r
++ struct omap3_processor_cx *cx = cpuidle_get_statedata(state);\r
++ struct timespec ts_preidle, ts_postidle, ts_idle;\r
++ struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd;\r
++ int neon_pwrst;\r
++\r
++ current_cx_state = *cx;\r
++\r
++ if (cx->type == OMAP3_STATE_C0) {\r
++ /* Do nothing for C0, not even a wfi */\r
++ return 0;\r
++ }\r
++\r
++ /* Used to keep track of the total time in idle */\r
++ getnstimeofday(&ts_preidle);\r
++\r
++ mpu_pd = pwrdm_lookup("mpu_pwrdm");\r
++ core_pd = pwrdm_lookup("core_pwrdm");\r
++ per_pd = pwrdm_lookup("per_pwrdm");\r
++ neon_pd = pwrdm_lookup("neon_pwrdm");\r
++\r
++ /* Reset previous power state registers */\r
++ pwrdm_clear_all_prev_pwrst(mpu_pd);\r
++ pwrdm_clear_all_prev_pwrst(neon_pd);\r
++ pwrdm_clear_all_prev_pwrst(core_pd);\r
++ pwrdm_clear_all_prev_pwrst(per_pd);\r
++\r
++ if (omap_irq_pending())\r
++ return 0;\r
++\r
++ neon_pwrst = pwrdm_read_pwrst(neon_pd);\r
++\r
++ /* Program MPU/NEON to target state */\r
++ if (cx->mpu_state < PWRDM_POWER_ON) {\r
++ if (neon_pwrst == PWRDM_POWER_ON) {\r
++ if (cx->mpu_state == PWRDM_POWER_RET)\r
++ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);\r
++ else if (cx->mpu_state == PWRDM_POWER_OFF)\r
++ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF);\r
++ }\r
++ pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);\r
++ }\r
++\r
++ /* Program CORE to target state */\r
++ if (cx->core_state < PWRDM_POWER_ON)\r
++ pwrdm_set_next_pwrst(core_pd, cx->core_state);\r
++\r
++ /* Execute ARM wfi */\r
++ omap_sram_idle();\r
++\r
++ /* Program MPU/NEON to ON */\r
++ if (cx->mpu_state < PWRDM_POWER_ON) {\r
++ if (neon_pwrst == PWRDM_POWER_ON)\r
++ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON);\r
++ pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON);\r
++ }\r
++\r
++ if (cx->core_state < PWRDM_POWER_ON)\r
++ pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON);\r
++\r
++ getnstimeofday(&ts_postidle);\r
++ ts_idle = timespec_sub(ts_postidle, ts_preidle);\r
++ return timespec_to_ns(&ts_idle);\r
++}\r
++\r
++/*\r
++ * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM\r
++ *\r
++ * This function checks for all the pre-requisites needed for OMAP3 to enter\r
++ * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired\r
++ * C state.\r
++ */\r
++static int omap3_enter_idle_bm(struct cpuidle_device *dev,\r
++ struct cpuidle_state *state)\r
++{\r
++ struct cpuidle_state *new_state = NULL;\r
++ int i, j;\r
++\r
++ if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {\r
++\r
++ /* Find current state in list */\r
++ for (i = 0; i < OMAP3_MAX_STATES; i++)\r
++ if (state == &dev->states[i])\r
++ break;\r
++ BUG_ON(i == OMAP3_MAX_STATES);\r
++\r
++ /* Back up to non 'CHECK_BM' state */\r
++ for (j = i - 1; j > 0; j--) {\r
++ struct cpuidle_state *s = &dev->states[j];\r
++\r
++ if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) {\r
++ new_state = s;\r
++ break;\r
++ }\r
++ }\r
++\r
++ pr_debug("%s: Bus activity: Entering %s (instead of %s)\n",\r
++ __FUNCTION__, new_state->name, state->name);\r
++ }\r
++\r
++ return omap3_enter_idle(dev, new_state ? : state);\r
++}\r
++\r
++DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);\r
++\r
++/* omap3_init_power_states - Initialises the OMAP3 specific C states.\r
++ * Below is the desciption of each C state.\r
++ *\r
++ C0 . System executing code\r
++ C1 . MPU WFI + Core active\r
++ C2 . MPU CSWR + Core active\r
++ C3 . MPU OFF + Core active\r
++ C4 . MPU CSWR + Core CSWR\r
++ C5 . MPU OFF + Core CSWR\r
++ C6 . MPU OFF + Core OFF\r
++ */\r
++void omap_init_power_states(void)\r
++{\r
++ /* C0 . System executing code */\r
++ omap3_power_states[0].valid = 1;\r
++ omap3_power_states[0].type = OMAP3_STATE_C0;\r
++ omap3_power_states[0].sleep_latency = 0;\r
++ omap3_power_states[0].wakeup_latency = 0;\r
++ omap3_power_states[0].threshold = 0;\r
++ omap3_power_states[0].mpu_state = PWRDM_POWER_ON;\r
++ omap3_power_states[0].core_state = PWRDM_POWER_ON;\r
++ omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID |\r
++ CPUIDLE_FLAG_SHALLOW;\r
++\r
++ /* C1 . MPU WFI + Core active */\r
++ omap3_power_states[1].valid = 1;\r
++ omap3_power_states[1].type = OMAP3_STATE_C1;\r
++ omap3_power_states[1].sleep_latency = 10;\r
++ omap3_power_states[1].wakeup_latency = 10;\r
++ omap3_power_states[1].threshold = 30;\r
++ omap3_power_states[1].mpu_state = PWRDM_POWER_ON;\r
++ omap3_power_states[1].core_state = PWRDM_POWER_ON;\r
++ omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID |\r
++ CPUIDLE_FLAG_SHALLOW;\r
++\r
++ /* C2 . MPU CSWR + Core active */\r
++ omap3_power_states[2].valid = 1;\r
++ omap3_power_states[2].type = OMAP3_STATE_C2;\r
++ omap3_power_states[2].sleep_latency = 50;\r
++ omap3_power_states[2].wakeup_latency = 50;\r
++ omap3_power_states[2].threshold = 300;\r
++ omap3_power_states[2].mpu_state = PWRDM_POWER_RET;\r
++ omap3_power_states[2].core_state = PWRDM_POWER_ON;\r
++ omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID |\r
++ CPUIDLE_FLAG_BALANCED;\r
++\r
++ /* C3 . MPU OFF + Core active */\r
++ omap3_power_states[3].valid = 0;\r
++ omap3_power_states[3].type = OMAP3_STATE_C3;\r
++ omap3_power_states[3].sleep_latency = 1500;\r
++ omap3_power_states[3].wakeup_latency = 1800;\r
++ omap3_power_states[3].threshold = 4000;\r
++ omap3_power_states[3].mpu_state = PWRDM_POWER_OFF;\r
++ omap3_power_states[3].core_state = PWRDM_POWER_RET;\r
++ omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID |\r
++ CPUIDLE_FLAG_BALANCED;\r
++\r
++ /* C4 . MPU CSWR + Core CSWR*/\r
++ omap3_power_states[4].valid = 1;\r
++ omap3_power_states[4].type = OMAP3_STATE_C4;\r
++ omap3_power_states[4].sleep_latency = 2500;\r
++ omap3_power_states[4].wakeup_latency = 7500;\r
++ omap3_power_states[4].threshold = 12000;\r
++ omap3_power_states[4].mpu_state = PWRDM_POWER_RET;\r
++ omap3_power_states[4].core_state = PWRDM_POWER_RET;\r
++ omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID |\r
++ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;\r
++\r
++ /* C5 . MPU OFF + Core CSWR */\r
++ omap3_power_states[5].valid = 0;\r
++ omap3_power_states[5].type = OMAP3_STATE_C5;\r
++ omap3_power_states[5].sleep_latency = 3000;\r
++ omap3_power_states[5].wakeup_latency = 8500;\r
++ omap3_power_states[5].threshold = 15000;\r
++ omap3_power_states[5].mpu_state = PWRDM_POWER_OFF;\r
++ omap3_power_states[5].core_state = PWRDM_POWER_RET;\r
++ omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID |\r
++ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;\r
++\r
++ /* C6 . MPU OFF + Core OFF */\r
++ omap3_power_states[6].valid = 0;\r
++ omap3_power_states[6].type = OMAP3_STATE_C6;\r
++ omap3_power_states[6].sleep_latency = 10000;\r
++ omap3_power_states[6].wakeup_latency = 30000;\r
++ omap3_power_states[6].threshold = 300000;\r
++ omap3_power_states[6].mpu_state = PWRDM_POWER_OFF;\r
++ omap3_power_states[6].core_state = PWRDM_POWER_OFF;\r
++ omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID |\r
++ CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM;\r
++}\r
++\r
++struct cpuidle_driver omap3_idle_driver = {\r
++ .name = "omap3_idle",\r
++ .owner = THIS_MODULE,\r
++};\r
++/*\r
++ * omap3_idle_init - Init routine for OMAP3 idle.\r
++ * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w\r
++ * with the valid set of states.\r
++ */\r
++int omap3_idle_init(void)\r
++{\r
++ int i, count = 0;\r
++ struct omap3_processor_cx *cx;\r
++ struct cpuidle_state *state;\r
++ struct cpuidle_device *dev;\r
++\r
++ omap_init_power_states();\r
++ cpuidle_register_driver(&omap3_idle_driver);\r
++\r
++ dev = &per_cpu(omap3_idle_dev, smp_processor_id());\r
++\r
++ for (i = 0; i < OMAP3_MAX_STATES; i++) {\r
++ cx = &omap3_power_states[i];\r
++ state = &dev->states[count];\r
++\r
++ if (!cx->valid)\r
++ continue;\r
++ cpuidle_set_statedata(state, cx);\r
++ state->exit_latency = cx->sleep_latency + cx->wakeup_latency;\r
++ state->target_residency = cx->threshold;\r
++ state->flags = cx->flags;\r
++ state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?\r
++ omap3_enter_idle_bm : omap3_enter_idle;\r
++ sprintf(state->name, "C%d", count+1);\r
++ count++;\r
++ }\r
++\r
++ if (!count)\r
++ return -EINVAL;\r
++ dev->state_count = count;\r
++\r
++ if (cpuidle_register_device(dev)) {\r
++ printk(KERN_ERR "%s: CPUidle register device failed\n",\r
++ __FUNCTION__);\r
++ return -EIO;\r
++ }\r
++\r
++ return 0;\r
++}\r
++__initcall(omap3_idle_init);\r
++#endif /* CONFIG_CPU_IDLE */\r
+Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h\r
+===================================================================\r
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000\r
++++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h 2008-06-09 20:15:39.569121361 +0530\r
+@@ -0,0 +1,51 @@\r
++/*\r
++ * linux/arch/arm/mach-omap2/cpuidle34xx.h\r
++ *\r
++ * OMAP3 cpuidle structure definitions\r
++ *\r
++ * Copyright (C) 2007-2008 Texas Instruments, Inc.\r
++ * Written by Rajendra Nayak <rnayak@ti.com>\r
++ *\r
++ * This program is free software; you can redistribute it and/or modify\r
++ * it under the terms of the GNU General Public License version 2 as\r
++ * published by the Free Software Foundation.\r
++ *\r
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\r
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\r
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\r
++ *\r
++ * History:\r
++ *\r
++ */\r
++\r
++#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX\r
++#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX\r
++\r
++#define OMAP3_MAX_STATES 7\r
++#define OMAP3_STATE_C0 0 /* C0 - System executing code */\r
++#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */\r
++#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */\r
++#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */\r
++#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */\r
++#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */\r
++#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */\r
++\r
++extern void omap_sram_idle(void);\r
++extern int omap3_irq_pending(void);\r
++\r
++struct omap3_processor_cx {\r
++ u8 valid;\r
++ u8 type;\r
++ u32 sleep_latency;\r
++ u32 wakeup_latency;\r
++ u32 mpu_state;\r
++ u32 core_state;\r
++ u32 threshold;\r
++ u32 flags;\r
++};\r
++\r
++void omap_init_power_states(void);\r
++int omap3_idle_init(void);\r
++\r
++#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */\r
++\r
+Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c\r
+===================================================================\r
+--- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:15:33.855303920 +0530\r
++++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:16:20.976798343 +0530\r
+@@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle\r
+ return IRQ_HANDLED;\r
+ }\r
+ \r
+-static void omap_sram_idle(void)\r
++void omap_sram_idle(void)\r
+ {\r
+ /* Variable to tell what needs to be saved and restored\r
+ * in omap_sram_idle*/\r
+@@ -156,6 +156,7 @@ static void omap_sram_idle(void)\r
+ \r
+ mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);\r
+ switch (mpu_next_state) {\r
++ case PWRDM_POWER_ON:\r
+ case PWRDM_POWER_RET:\r
+ /* No need to save context */\r
+ save_state = 0;\r
+@@ -386,7 +387,9 @@ int __init omap3_pm_init(void)\r
+ \r
+ prcm_setup_regs();\r
+ \r
++#ifndef CONFIG_CPU_IDLE\r
+ pm_idle = omap3_pm_idle;\r
++#endif\r
+ \r
+ err1:\r
+ return ret;\r
+Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c\r
+===================================================================\r
+--- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:33.856303888 +0530\r
++++ linux-omap-2.6/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:39.570121329 +0530\r
+@@ -58,6 +58,11 @@ static void cpuidle_idle_call(void)\r
+ return;\r
+ }\r
+ \r
++#ifdef CONFIG_ARCH_OMAP3\r
++ local_irq_disable();\r
++ local_fiq_disable();\r
++#endif\r
++\r
+ /* ask the governor for the next state */\r
+ next_state = cpuidle_curr_governor->select(dev);\r
+ if (need_resched())\r
+@@ -70,6 +75,11 @@ static void cpuidle_idle_call(void)\r
+ target_state->time += (unsigned long long)dev->last_residency;\r
+ target_state->usage++;\r
+ \r
++#ifdef CONFIG_ARCH_OMAP3\r
++ local_irq_enable();\r
++ local_fiq_enable();\r
++#endif\r
++\r
+ /* give the governor an opportunity to reflect on the outcome */\r
+ if (cpuidle_curr_governor->reflect)\r
+ cpuidle_curr_governor->reflect(dev);\r
+\r
+--\r
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in\r
+the body of a message to majordomo@vger.kernel.org\r
+More majordomo info at http://vger.kernel.org/majordomo-info.html\r
+\r
git.openpandora.org / openembedded.git / commitdiff