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staging: tidspbridge: MMU2 registers are limited to 32-bit data access
authorVladimir Zapolskiy <vz@mleia.com>
Wed, 19 Oct 2011 19:39:12 +0000 (22:39 +0300)
committerGreg Kroah-Hartman <gregkh@suse.de>
Wed, 19 Oct 2011 20:42:49 +0000 (13:42 -0700)
According to OMAP3 TRM access to MMU registers shall be strictly 32-bit
aligned.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Omar Ramirez Luna <omar.ramirez@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

No differences found
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