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drm/i915: PLL registers need an offset on VLV
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 25 Jan 2013 19:44:41 +0000 (21:44 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Sat, 26 Jan 2013 16:29:45 +0000 (17:29 +0100)
v2: Dropped the clock gating registers

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

No differences found
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