This should only be required on MIPS where CFG_SYS_SDRAM_BASE is still
being used as virtual address.
+config PCI_BRIDGE_MEM_ALIGNMENT
+ hex "Alignment boundary of PCI memory resource allocation"
+ default 0x10000 if TARGET_BOSTON
+ default 0x100000
+ help
+ Specify a boundary for alignment of PCI memory resource allocation,
+ this is normally 0x100000 (1MB) but can be reduced to accommodate
+ hardware with tight bridge range if hardware allows.
+
config PCI_SRIOV
bool "Enable Single Root I/O Virtualization support for PCI"
help
dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
if (pci_mem) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_mem, 0x100000);
+ /* Round memory allocator */
+ pciauto_region_align(pci_mem, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT);
/*
* Set up memory and I/O filter limits, assume 32-bit
}
if (pci_prefetch) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_prefetch, 0x100000);
+ /* Round memory allocator */
+ pciauto_region_align(pci_prefetch, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT);
/*
* Set up memory and I/O filter limits, assume 32-bit
dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - dev_seq(ctlr));
if (pci_mem) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_mem, 0x100000);
+ /* Round memory allocator */
+ pciauto_region_align(pci_mem, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT);
dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
((pci_mem->bus_lower - 1) >> 16) &
&prefechable_64);
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_prefetch, 0x100000);
+ /* Round memory allocator */
+ pciauto_region_align(pci_prefetch, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT);
dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
(((pci_prefetch->bus_lower - 1) >> 16) &