sunxi: a523: Re-use H6/H616 DRAM size detection method

The H6 and H616 DRAM initialisation code recently gained a joint and
improved size detection routine, which helped to avoid the occasional
DRAM size misdetection.

Use the same code for the A523 DRAM initialisation as well, which
suffers from the same misdetection at times.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Chen-Yu Tsai <wens@kernel.org>

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 579530f..9c79b55 100644 (file)
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -47,6 +47,6 @@ obj-$(CONFIG_DRAM_SUN50I_H616)        += dram_sun50i_h616.o dram_dw_helpers.o
 obj-$(CONFIG_DRAM_SUN50I_H616) += dram_timings/
 obj-$(CONFIG_DRAM_SUN50I_A133) += dram_sun50i_a133.o
 obj-$(CONFIG_DRAM_SUN50I_A133) += dram_timings/
-obj-$(CONFIG_MACH_SUN55I_A523) += dram_sun55i_a523.o
+obj-$(CONFIG_MACH_SUN55I_A523) += dram_sun55i_a523.o dram_dw_helpers.o
 obj-$(CONFIG_DRAM_SUN55I_A523) += dram_timings/
 endif

diff --git a/arch/arm/mach-sunxi/dram_sun55i_a523.c b/arch/arm/mach-sunxi/dram_sun55i_a523.c
index 30bbeb4..1ffb628 100644 (file)
--- a/arch/arm/mach-sunxi/dram_sun55i_a523.c
+++ b/arch/arm/mach-sunxi/dram_sun55i_a523.c
@@ -12,6 +12,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/dram.h>
+#include <asm/arch/dram_dw_helpers.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/prcm.h>
 #include <linux/bitops.h>
@@ -1387,91 +1388,14 @@ static bool mctl_ctrl_init(const struct dram_para *para,
        return true;
 }
 
-static bool mctl_core_init(const struct dram_para *para,
-                          const struct dram_config *config)
+bool mctl_core_init(const struct dram_para *para,
+                   const struct dram_config *config)
 {
        mctl_sys_init(config->clk);
 
        return mctl_ctrl_init(para, config);
 }
 
-static void mctl_auto_detect_rank_width(const struct dram_para *para,
-                                       struct dram_config *config)
-{
-       /* this is minimum size that it's supported */
-       config->cols = 8;
-       config->rows = 13;
-
-       /*
-        * Strategy here is to test most demanding combination first and least
-        * demanding last, otherwise HW might not be fully utilized. For
-        * example, half bus width and rank = 1 combination would also work
-        * on HW with full bus width and rank = 2, but only 1/4 RAM would be
-        * visible.
-        */
-
-       debug("testing 32-bit width, rank = 2\n");
-       config->bus_full_width = 1;
-       config->ranks = 2;
-       if (mctl_core_init(para, config))
-               return;
-
-       debug("testing 32-bit width, rank = 1\n");
-       config->bus_full_width = 1;
-       config->ranks = 1;
-       if (mctl_core_init(para, config))
-               return;
-
-       debug("testing 16-bit width, rank = 2\n");
-       config->bus_full_width = 0;
-       config->ranks = 2;
-       if (mctl_core_init(para, config))
-               return;
-
-       debug("testing 16-bit width, rank = 1\n");
-       config->bus_full_width = 0;
-       config->ranks = 1;
-       if (mctl_core_init(para, config))
-               return;
-
-       panic("This DRAM setup is currently not supported.\n");
-}
-
-static void mctl_auto_detect_dram_size(const struct dram_para *para,
-                                      struct dram_config *config)
-{
-       /* detect row address bits */
-       config->cols = 8;
-       config->rows = 16;
-       mctl_core_init(para, config);
-
-       for (config->rows = 13; config->rows < 16; config->rows++) {
-               /* 8 banks, 8 bit per byte and 16/32 bit width */
-               if (mctl_mem_matches((1 << (config->rows + config->cols +
-                                           4 + config->bus_full_width))))
-                       break;
-       }
-
-       /* detect column address bits */
-       config->cols = 11;
-       mctl_core_init(para, config);
-
-       for (config->cols = 8; config->cols < 11; config->cols++) {
-               /* 8 bits per byte and 16/32 bit width */
-               if (mctl_mem_matches(1 << (config->cols + 1 +
-                                          config->bus_full_width)))
-                       break;
-       }
-}
-
-static unsigned long long mctl_calc_size(const struct dram_config *config)
-{
-       u8 width = config->bus_full_width ? 4 : 2;
-
-       /* 8 banks */
-       return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks;
-}
-
 static const struct dram_para para = {
 #ifdef CONFIG_SUNXI_DRAM_A523_DDR3
        .type = SUNXI_DRAM_TYPE_DDR3,