pwm: mediatek: add pwm support for MediaTek MT7987 SoC

This patch adds pwm support for MediaTek MT7987 SoC.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

diff --git a/arch/arm/dts/mt7987-pinctrl.dtsi b/arch/arm/dts/mt7987-pinctrl.dtsi
index b5e643f..dfde212 100644 (file)
--- a/arch/arm/dts/mt7987-pinctrl.dtsi
+++ b/arch/arm/dts/mt7987-pinctrl.dtsi
@@ -191,6 +191,20 @@
                };
        };
 
+       pwm_pins: pwm-pins {
+               mux {
+                       /*
+                        * - pwm0   : PWM0@PIN13
+                        * - pwm1_0 : PWM1@PIN7  (share with JTAG)
+                        *   pwm1_1 : PWM1@PIN43 (share with i2c0)
+                        * - pwm2_0 : PWM2@PIN12 (share with PCM)
+                        *   pwm2_1 : PWM2@PIN44 (share with i2c0)
+                        */
+                       function = "pwm";
+                       groups = "pwm0";
+               };
+       };
+
        uart1_pins: uart1-pins {
                mux {
                        function = "uart";

diff --git a/arch/arm/dts/mt7987.dtsi b/arch/arm/dts/mt7987.dtsi
index fd1585f..4c1d597 100644 (file)
--- a/arch/arm/dts/mt7987.dtsi
+++ b/arch/arm/dts/mt7987.dtsi
@@ -389,21 +389,15 @@
                };
 
                pwm: pwm@10048000 {
-                       compatible = "mediatek,mt7988-pwm";
+                       compatible = "mediatek,mt7987-pwm";
                        reg = <0 0x10048000 0 0x1000>;
                        #pwm-cells = <2>;
                        clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
                                 <&infracfg CLK_INFRA_66M_PWM_HCK>,
-                                <&clkxtal>,
-                                <&clkxtal>,
-                                <&clkxtal>,
-                                <&clkxtal>,
-                                <&clkxtal>,
-                                <&clkxtal>,
-                                <&clkxtal>,
-                                <&clkxtal>;
-                       clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
-                                     "pwm4","pwm5","pwm6","pwm7","pwm8";
+                                <&infracfg CLK_INFRA_66M_PWM_HCK>,
+                                <&infracfg CLK_INFRA_66M_PWM_HCK>,
+                                <&infracfg CLK_INFRA_66M_PWM_HCK>;
+                       clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
                        status = "disabled";
                };
 

diff --git a/arch/arm/dts/mt7987a.dtsi b/arch/arm/dts/mt7987a.dtsi
index 028f563..bf53e89 100644 (file)
--- a/arch/arm/dts/mt7987a.dtsi
+++ b/arch/arm/dts/mt7987a.dtsi
@@ -59,6 +59,8 @@
 };
 
 &pwm {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pwm_pins>;
        status = "okay";
 };
 

diff --git a/drivers/pwm/pwm-mtk.c b/drivers/pwm/pwm-mtk.c
index 5cf2eba..898e353 100644 (file)
--- a/drivers/pwm/pwm-mtk.c
+++ b/drivers/pwm/pwm-mtk.c
@@ -30,6 +30,7 @@
 enum mtk_pwm_reg_ver {
        PWM_REG_V1,
        PWM_REG_V2,
+       PWM_REG_V3,
 };
 
 static const unsigned int mtk_pwm_reg_offset_v1[] = {
@@ -40,6 +41,10 @@ static const unsigned int mtk_pwm_reg_offset_v2[] = {
        0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
 };
 
+static const unsigned int mtk_pwm_reg_offset_v3[] = {
+       0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x600, 0x700, 0x0800
+};
+
 struct mtk_pwm_soc {
        unsigned int num_pwms;
        bool pwm45_fixup;
@@ -60,6 +65,10 @@ static void mtk_pwm_w32(struct udevice *dev, uint channel, uint reg, uint val)
        u32 offset;
 
        switch (priv->soc->reg_ver) {
+       case PWM_REG_V3:
+               offset = mtk_pwm_reg_offset_v3[channel];
+               break;
+
        case PWM_REG_V2:
                offset = mtk_pwm_reg_offset_v2[channel];
                break;
@@ -203,6 +212,12 @@ static const struct mtk_pwm_soc mt7986_data = {
        .reg_ver = PWM_REG_V1,
 };
 
+static const struct mtk_pwm_soc mt7987_data = {
+       .num_pwms = 3,
+       .pwm45_fixup = false,
+       .reg_ver = PWM_REG_V3,
+};
+
 static const struct mtk_pwm_soc mt7988_data = {
        .num_pwms = 8,
        .pwm45_fixup = false,
@@ -215,6 +230,7 @@ static const struct udevice_id mtk_pwm_ids[] = {
        { .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
        { .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
        { .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
+       { .compatible = "mediatek,mt7987-pwm", .data = (ulong)&mt7987_data },
        { .compatible = "mediatek,mt7988-pwm", .data = (ulong)&mt7988_data },
        { }
 };