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MIPS: lantiq: enable pci clk conditional for xrx200 SoC
author
John Crispin
<blogic@openwrt.org>
Thu, 16 Aug 2012 08:25:42 +0000
(08:25 +0000)
committer
John Crispin
<blogic@openwrt.org>
Wed, 22 Aug 2012 22:08:18 +0000
(
00:08
+0200)
The xrx200 SoC family has the same PCI clock register layout as the AR9.
Enable the same quirk as for AR9
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4235/
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git.openpandora.org / pandora-kernel.git / commitdiff