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be2net: memory barrier fixes on IBM p7 platform
authorSathya Perla <sathyap@serverengines.com>
Tue, 29 Jun 2010 00:11:17 +0000 (00:11 +0000)
committerDavid S. Miller <davem@davemloft.net>
Wed, 30 Jun 2010 20:26:42 +0000 (13:26 -0700)
The ibm p7 architecure seems to reorder memory accesses more
aggressively than previous ppc64 architectures. This requires memory
barriers to ensure that rx/tx doorbells are pressed only after
memory to be DMAed is written.

Signed-off-by: Sathya Perla <sathyap@serverengines.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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