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mmc: sdhci: add DDR50 1.8V mode support for BayTrail eMMC Controller
authorMaurice Petallo <mauricex.r.petallo@intel.com>
Tue, 8 Jul 2014 11:11:01 +0000 (19:11 +0800)
committerUlf Hansson <ulf.hansson@linaro.org>
Thu, 10 Jul 2014 12:58:29 +0000 (14:58 +0200)
This is to enable DDR50 bus speed mode with 1.8V signaling capability
for BayTrail ACPI and PCI mode eMMC Controller.

Signed-off-by: Maurice Petallo <mauricex.r.petallo@intel.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

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