serial: msm: Reset after writing to DMEN

According to the documentation of the UART controller in the APQ8016E TRM,
clearing bits inside UARTDM_DMEN requires resetting the transmitter and/or
receiver. We do reset inside uart_dm_init(), but before writing to
UARTDM_DMEN. This doesn't seem to cause problems in practice, but let's
move the reset to the end of uart_dm_init() to better match the
recommendations in the documentation.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Tested-by: Alexey Minnekhanov <alexeymin@minlexx.ru>
Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250908-db410c-autoboot-fixes-v2-4-316ed98e0143@linaro.org
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>

diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index aa4d10e..5523ec4 100644 (file)
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -219,11 +219,12 @@ static void uart_dm_init(struct msm_serial_data *priv)
        /* Enable RS232 flow control to support RS232 db9 connector */
        writel(UARTDM_MR1_RX_RDY_CTL, priv->base + UARTDM_MR1);
        writel(UARTDM_MR2_8_N_1_MODE, priv->base + UARTDM_MR2);
-       writel(UARTDM_CR_CMD_RESET_RX, priv->base + UARTDM_CR);
-       writel(UARTDM_CR_CMD_RESET_TX, priv->base + UARTDM_CR);
 
        /* Make sure BAM/single character mode is disabled */
        writel(0x0, priv->base + UARTDM_DMEN);
+
+       writel(UARTDM_CR_CMD_RESET_RX, priv->base + UARTDM_CR);
+       writel(UARTDM_CR_CMD_RESET_TX, priv->base + UARTDM_CR);
 }
 static int msm_serial_probe(struct udevice *dev)
 {