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netxen: cache align register map table
authorDhananjay Phadke <dhananjay@netxen.com>
Tue, 7 Apr 2009 22:50:48 +0000 (22:50 +0000)
committerDavid S. Miller <davem@davemloft.net>
Wed, 8 Apr 2009 22:58:31 +0000 (15:58 -0700)
Aligning register offset translation table imporves performance
on rx side.

Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

No differences found
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