export KDIR=$(KERNELDIR)
export BUILD = release
+export TI_PLATFORM ?= omap3
+export OMAPES ?= 3.x
export KBUILD_EXTRA_SYMBOLS = `pwd`/services4/srvkm/env/linux/kbuild/Module.symvers
SysAcquireData(&psSysData);
- ui32SGXRevision = SGX_CORE_REV;
+ ui32SGXRevision = cpu_is_omap3630() ? 125 : 121;
ui32MaxStrLen = 99;
i32Count = OSSNPrintf(aszVersionString, ui32MaxStrLen + 1,
#if !defined(SGX_DYNAMIC_TIMING_INFO)
/* Set up timing information*/
psTimingInfo = &gsSGXDeviceMap.sTimingInfo;
- psTimingInfo->ui32CoreClockSpeed = SYS_SGX_CLOCK_SPEED;
+ psTimingInfo->ui32CoreClockSpeed = cpu_is_omap3630() ? 200000000 : 110666666;
psTimingInfo->ui32HWRecoveryFreq = SYS_SGX_HWRECOVERY_TIMEOUT_FREQ;
#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT)
psTimingInfo->bEnableActivePM = IMG_TRUE;
#define SYS_OMAP3430_SGX_REGS_SYS_PHYS_BASE 0x50000000
-#define SYS_OMAP3430_SGX_REGS_SIZE 0x4000
+
+#define SYS_OMAP3430_SGX_REGS_SIZE 0x10000
#define SYS_OMAP3430_SGX_IRQ 21 /* OMAP4 IRQ's are offset by 32 */
extern struct platform_device *gpsPVRLDMDev;
#endif
+
+#undef SYS_SGX_CLOCK_SPEED
+#define SYS_SGX_CLOCK_SPEED sgx_clock_speed
+static int sgx_clock_speed;
+
static PVRSRV_ERROR PowerLockWrap(SYS_SPECIFIC_DATA *psSysSpecData, IMG_BOOL bTryLock)
{
if (!in_interrupt())
}
#endif
#endif
+
+#if 1
+ {
+ static int logged;
+ IMG_UINT32 rate = clk_get_rate(psSysSpecData->psSGX_FCK);
+ if (!logged) {
+ printk(KERN_INFO "SGX clock rate: %u\n", rate);
+ logged = 1;
+ }
+ }
+#endif
+
#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI)
#if defined(SYS_OMAP_HAS_DVFS_FRAMEWORK)
{
mutex_init(&psSysSpecData->sPowerLock);
atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
-
- psCLK = clk_get(NULL, SGX_PARENT_CLOCK);
+
+ SYS_SGX_CLOCK_SPEED = cpu_is_omap3630() ? 200000000 : 110666666;
+
+ psCLK = clk_get(NULL, SGX_PARENT_CLOCK);
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSsystemClocks: Couldn't get Core Clock"));