ARM: tegra124: clock: implement PLLD2 support

PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>

diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h
index 9f53125..055948e 100644 (file)
--- a/arch/arm/include/asm/arch-tegra124/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h
@@ -24,6 +24,7 @@ enum clock_id {
        CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
        CLOCK_ID_EPCI,
        CLOCK_ID_SFROM32KHZ,
+       CLOCK_ID_DISPLAY2,
        CLOCK_ID_DP,    /* Special for Tegra124 */
 
        /* These are the base clocks (inputs to the Tegra SoC) */
@@ -37,7 +38,6 @@ enum clock_id {
         * These are clock IDs that are used in table clock_source[][]
         * but will not be assigned as a clock source for any peripheral.
         */
-       CLOCK_ID_DISPLAY2,
        CLOCK_ID_CGENERAL2,
        CLOCK_ID_CGENERAL3,
        CLOCK_ID_MEMORY2,

diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index 4ac0c10..0ea212f 100644 (file)
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -598,6 +598,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
          .lock_ena = 9,  .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 },     /* PLLE */
        { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
          .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
+       { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
+         .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */
        { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 20,  .p_mask = 0xF,
          .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 },   /* PLLDP */
 };
@@ -852,6 +854,9 @@ enum clock_id clk_id_to_pll_id(int clk_id)
        case TEGRA124_CLK_PLL_D:
        case TEGRA124_CLK_PLL_D_OUT0:
                return CLOCK_ID_DISPLAY;
+       case TEGRA124_CLK_PLL_D2:
+       case TEGRA124_CLK_PLL_D2_OUT0:
+               return CLOCK_ID_DISPLAY2;
        case TEGRA124_CLK_PLL_X:
                return CLOCK_ID_XCPU;
        case TEGRA124_CLK_PLL_E:
@@ -1194,6 +1199,8 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
        case CLOCK_ID_EPCI:
        case CLOCK_ID_SFROM32KHZ:
                return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
+       case CLOCK_ID_DISPLAY2:
+               return &clkrst->plld2;
        case CLOCK_ID_DP:
                return &clkrst->plldp;
        default: