Overo: Add support for Hynix POP (512MB DDR, 512MB NAND)

diff --git a/board/overo/overo.c b/board/overo/overo.c
index 68ee13c..8df53e5 100644 (file)
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -452,6 +452,17 @@ void config_3430sdram_ddr(void)
                __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
                __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
                break;
+       case 2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
+               __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
+               __raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_0);
+               __raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_1);
+               __raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
+               __raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
+               __raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
+               __raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
+               __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
+               __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
+               break;
        default:
                __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
                __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);

diff --git a/drivers/k9f1g08r0a.c b/drivers/k9f1g08r0a.c
index e0b1af5..988533c 100644 (file)
--- a/drivers/k9f1g08r0a.c
+++ b/drivers/k9f1g08r0a.c
@@ -42,6 +42,7 @@
  */
 #define MT29F1G_MFR            0x2c  /* Micron */
 #define MT29F1G_MFR2           0x20  /* numonyx */
+#define MT29F1G_MFR3           0xad  /* Hynix */
 #define MT29F1G_ID             0xa1  /* x8, 1GiB */
 #define MT29F2G_ID             0xba  /* x16, 2GiB */
 #define MT29F4G_ID             0xbc  /* x16, 4GiB */
@@ -206,7 +207,7 @@ int nand_chip()
 
        NAND_DISABLE_CE();
 
-       if (((mfr == MT29F1G_MFR || mfr == MT29F1G_MFR2) &&
+       if (((mfr == MT29F1G_MFR || mfr == MT29F1G_MFR2 || mfr == MT29F1G_MFR3) &&
                (id == MT29F1G_ID || id == MT29F2G_ID || id == MT29F4G_ID)) ||
             (mfr == K9F1G08R0A_MFR && (id == K9F1G08R0A_ID))) {
                return 0;

diff --git a/include/asm/arch-omap3/mem.h b/include/asm/arch-omap3/mem.h
index 63cdba1..284c665 100644 (file)
--- a/include/asm/arch-omap3/mem.h
+++ b/include/asm/arch-omap3/mem.h
@@ -74,6 +74,7 @@ typedef enum {
 #define SDP_SDRC_MDCFG_0_DDR   (0x02584019|B_ALL)
 #define SDP_SDRC_MDCFG_0_DDR_MICRON_XM (0x03588019|B_ALL)
 #define SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM        (0x04590019|B_ALL)
+#define SDP_SDRC_MDCFG_0_DDR_HYNIX     (0x03588019|B_ALL)
 #endif
 
 #define SDP_SDRC_MR_0_DDR              0x00000032
@@ -295,6 +296,46 @@ typedef enum {
 #define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | (NUMONYX_XSR_165 << 0)) | \
                                (NUMONYX_TXP_165 << 8) | (NUMONYX_TWTR_165 << 16)
 
+/*
+ * Hynix part of Overo (165MHz optimized) 6.06ns
+ *   ACTIMA
+ *     ACTIMA
+ *        TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
+ *        TDPL (Twr) = 15/6       = 2.5 -> 3
+ *        TRRD = 12/6     = 2
+ *        TRCD = 18/6     = 3
+ *        TRP = 18/6      = 3
+ *        TRAS = 42/6     = 7
+ *        TRC = 60/6      = 10
+ *        TRFC = 97.5/6    = 17
+ *     ACTIMB
+ *        TWTR = 1
+ *        TCKE = 1
+ *        TXP = 1+1
+ *        XSR = 140/6 = 24
+ */
+#define HYNIX_TDAL_165   6
+#define HYNIX_TDPL_165   3
+#define HYNIX_TRRD_165   2
+#define HYNIX_TRCD_165   3
+#define HYNIX_TRP_165    3
+#define HYNIX_TRAS_165   7
+#define HYNIX_TRC_165   10
+#define HYNIX_TRFC_165  21
+#define HYNIX_V_ACTIMA_165 ((HYNIX_TRFC_165 << 27) | \
+               (HYNIX_TRC_165 << 22) | (HYNIX_TRAS_165 << 18) | \
+               (HYNIX_TRP_165 << 15) | (HYNIX_TRCD_165 << 12) | \
+               (HYNIX_TRRD_165 << 9) | (HYNIX_TDPL_165 << 6) | \
+               (HYNIX_TDAL_165))
+
+#define HYNIX_TWTR_165   1
+#define HYNIX_TCKE_165   1
+#define HYNIX_TXP_165    2
+#define HYNIX_XSR_165    24
+#define HYNIX_V_ACTIMB_165 ((HYNIX_TCKE_165 << 12) | \
+               (HYNIX_XSR_165 << 0) | (HYNIX_TXP_165 << 8) | \
+               (HYNIX_TWTR_165 << 16))
+
 /* New and compatability speed defines */
 #if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B)
 # define L3_100MHZ   /* Use with <= 100MHz SDRAM */