regulator: rzg2l-usbphy: Add new driver
authorPaul Barker <paul.barker.ct@bp.renesas.com>
Tue, 11 Mar 2025 20:57:44 +0000 (20:57 +0000)
committerMarek Vasut <marek.vasut+renesas@mailbox.org>
Wed, 19 Mar 2025 02:36:19 +0000 (03:36 +0100)
Add a new regulator driver to control the USB VBUS supply on the Renesas
RZ/G2L and related SoCs.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
drivers/power/regulator/Kconfig
drivers/power/regulator/Makefile
drivers/power/regulator/rzg2l-usbphy-regulator.c [new file with mode: 0644]

index 958f337..8f102a9 100644 (file)
@@ -478,3 +478,11 @@ config DM_REGULATOR_TPS65219
        features for REGULATOR TPS65219 and the family of TPS65219 PMICs.
        TPS65219 series of PMICs have 3 single phase BUCKs & 4 LDOs.
        The driver implements get/set api for value and enable.
+
+config REGULATOR_RZG2L_USBPHY
+       bool "Enable driver for RZ/G2L USB PHY VBUS supply"
+       depends on DM_REGULATOR
+       help
+         Enable this option to support controlling the VBUS supply in
+         the USB PHY peripheral of the Renesas RZ/G2L SoC. This option
+         is required in order to use the USB OTG port.
index ca6c89d..4382d4b 100644 (file)
@@ -42,3 +42,4 @@ obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o
 obj-$(CONFIG_DM_REGULATOR_SCMI) += scmi_regulator.o
 obj-$(CONFIG_$(XPL_)DM_REGULATOR_ANATOP) += anatop_regulator.o
 obj-$(CONFIG_DM_REGULATOR_TPS65219) += tps65219_regulator.o
+obj-$(CONFIG_REGULATOR_RZG2L_USBPHY) += rzg2l-usbphy-regulator.o
diff --git a/drivers/power/regulator/rzg2l-usbphy-regulator.c b/drivers/power/regulator/rzg2l-usbphy-regulator.c
new file mode 100644 (file)
index 0000000..451f04c
--- /dev/null
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Renesas Electronics Corporation
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <power/regulator.h>
+#include <renesas/rzg2l-usbphy.h>
+
+#define VBENCTL                        0x03c
+#define VBENCTL_VBUS_SEL       BIT(0)
+
+static int rzg2l_usbphy_regulator_set_enable(struct udevice *dev, bool enable)
+{
+       struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev->parent);
+
+       if (enable)
+               clrbits_le32(priv->regs + VBENCTL, VBENCTL_VBUS_SEL);
+       else
+               setbits_le32(priv->regs + VBENCTL, VBENCTL_VBUS_SEL);
+
+       return 0;
+}
+
+static int rzg2l_usbphy_regulator_get_enable(struct udevice *dev)
+{
+       struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev->parent);
+
+       return !!readl(priv->regs + VBENCTL) & VBENCTL_VBUS_SEL;
+}
+
+static const struct dm_regulator_ops rzg2l_usbphy_regulator_ops = {
+       .get_enable = rzg2l_usbphy_regulator_get_enable,
+       .set_enable = rzg2l_usbphy_regulator_set_enable,
+};
+
+U_BOOT_DRIVER(rzg2l_usbphy_regulator) = {
+       .name = "rzg2l_usbphy_regulator",
+       .id = UCLASS_REGULATOR,
+       .ops = &rzg2l_usbphy_regulator_ops,
+};