e1000e: Correct link check logic for 82571 serdes
authorTushar Dave <tushar.n.dave@intel.com>
Thu, 12 Jul 2012 08:56:56 +0000 (08:56 +0000)
committerBen Hutchings <ben@decadent.org.uk>
Wed, 25 Jul 2012 03:11:23 +0000 (04:11 +0100)
commit d0efa8f23a644f7cb7d1f8e78dd9a223efa412a3 upstream.

SYNCH bit and IV bit of RXCW register are sticky. Before examining these bits,
RXCW should be read twice to filter out one-time false events and have correct
values for these bits. Incorrect values of these bits in link check logic can
cause weird link stability issues if auto-negotiation fails.

Reported-by: Dean Nelson <dnelson@redhat.com>
Signed-off-by: Tushar Dave <tushar.n.dave@intel.com>
Reviewed-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>

No differences found