* Copyright 2018 NXP
*/
-#define MIDR_PARTNUM_CORTEX_A35 0xD04
-#define MIDR_PARTNUM_CORTEX_A53 0xD03
-#define MIDR_PARTNUM_CORTEX_A72 0xD08
-#define MIDR_PARTNUM_SHIFT 0x4
-#define MIDR_PARTNUM_MASK (0xFFF << 0x4)
+#define MIDR_PARTNUM_CORTEX_A35 0xD04
+#define MIDR_PARTNUM_CORTEX_A53 0xD03
+#define MIDR_PARTNUM_CORTEX_A72 0xD08
+#define MIDR_PARTNUM_SHIFT 0x4
+#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT)
static inline unsigned int read_midr(void)
{
return val;
}
-#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \
- MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35)
-#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \
- MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53)
-#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\
- MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72)
+#define is_cortex_a(__n) \
+ static inline int is_cortex_a##__n(void) \
+ { \
+ unsigned int midr = read_midr(); \
+ midr &= MIDR_PARTNUM_MASK; \
+ midr >>= MIDR_PARTNUM_SHIFT; \
+ return midr == MIDR_PARTNUM_CORTEX_A##__n; \
+ }
+
+is_cortex_a(35)
+is_cortex_a(53)
+is_cortex_a(72)