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drm/i915: Include TLB miss overhead for computing WM
author
Chris Wilson
<chris@chris-wilson.co.uk>
Sat, 8 Jan 2011 09:02:21 +0000
(09:02 +0000)
committer
Chris Wilson
<chris@chris-wilson.co.uk>
Tue, 11 Jan 2011 20:44:54 +0000
(20:44 +0000)
The docs recommend that if 8 display lines fit inside the FIFO buffer,
then the number of watermark entries should be increased to hide the
latency of filling the rest of the FIFO buffer.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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git.openpandora.org / pandora-kernel.git / commitdiff