x-load git: convert base SRC_URI to the new upstream + 5 patches from Salveti

* Make beagleboard use new URI

Signed-off-by: Koen Kooi <koen@openembedded.org>

diff --git a/recipes/x-load/x-load-git/0001-OMAP4-clocks-Enable-only-required-clks.patch b/recipes/x-load/x-load-git/0001-OMAP4-clocks-Enable-only-required-clks.patch
new file mode 100644 (file)
index 0000000..774f1e7
--- /dev/null
+++ b/recipes/x-load/x-load-git/0001-OMAP4-clocks-Enable-only-required-clks.patch
@@ -0,0 +1,265 @@
+From 94fee465a6d63b6f0551037fe14cec4410bb9af2 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Tue, 21 Dec 2010 11:55:01 -0200
+Subject: [PATCH 1/5] OMAP4: clocks: Enable only required clks
+
+X-loader untill now, was enabling all clks at bootup
+to help all modules to be functional at the kernel, even
+with drivers which do not handle clks well.
+Now that we are moving towards all drivers being adapted
+to request/release clks as expected, most of this code is
+useless and hence removed.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
+---
+ board/omap4430panda/clock.c |  225 ++++++++++++++++++++++---------------------
+ 1 files changed, 117 insertions(+), 108 deletions(-)
+
+diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
+index 792e5d6..149fc85 100644
+--- a/board/omap4430panda/clock.c
++++ b/board/omap4430panda/clock.c
+@@ -552,71 +552,73 @@ static void enable_all_clocks(void)
+ {
+       volatile int regvalue = 0;
+ 
+-      /* Enable Ducati clocks */
+-      sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
+-      sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
+-
+-      wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
+-      //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY);
+-
+-      /* Enable ivahd and sl2 clocks */
+-      sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
+-      sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1);
+-      sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2);
+-
+-      wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
+-
+-      /* wait for ivahd to become accessible */
+-      //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY);
+-      /* wait for sl2 to become accessible */
+-      //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY);
+-
+-      /* Enable Tesla clocks */
+-      sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
+-      sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
+-
+-      wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
+-
+-      /* wait for tesla to become accessible */
+-      //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY);
+-
+-      /* TODO: Some hack needed by MM: Clean this */
+-      #if 0 /* Doesn't work on some Zebu */
+-      *(volatile int*)0x4a306910 = 0x00000003;
+-      *(volatile int*)0x550809a0 = 0x00000001;
+-      *(volatile int*)0x55080a20 = 0x00000007;
+-      #endif
+-
+-      /* ABE clocks */
+-      sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
+-      sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
+-      //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY);
+-      sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
+-      //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY);
+-      sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
+-      //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY);
+-      sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
+-      //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY);
+-      sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
+-      //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY);
+-      sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
+-      //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY);
+-      sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
+-      //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY);
+-      sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
+-      //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY);
+-      sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
+-      //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY);
+-      sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
+-      //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY);
+-      sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
+-      //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY);
+-      sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
+-      //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY);
+-      sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
+-      //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY);
+-      /* Disable sleep transitions */
+-      sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
++      if (omap_revision() == OMAP4430_ES1_0) {
++              /* Enable Ducati clocks */
++              sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
++              sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
++
++              wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
++              //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY);
++
++              /* Enable ivahd and sl2 clocks */
++              sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
++              sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1);
++              sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2);
++
++              wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
++
++              /* wait for ivahd to become accessible */
++              //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY);
++              /* wait for sl2 to become accessible */
++              //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY);
++
++              /* Enable Tesla clocks */
++              sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
++              sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
++
++              wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
++
++              /* wait for tesla to become accessible */
++              //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY);
++
++              /* TODO: Some hack needed by MM: Clean this */
++              #if 0 /* Doesn't work on some Zebu */
++              *(volatile int*)0x4a306910 = 0x00000003;
++              *(volatile int*)0x550809a0 = 0x00000001;
++              *(volatile int*)0x55080a20 = 0x00000007;
++              #endif
++
++              /* ABE clocks */
++              sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
++              sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
++              //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY);
++              sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
++              //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY);
++              sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
++              //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY);
++              sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
++              //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY);
++              sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
++              //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY);
++              sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
++              //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY);
++              sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
++              //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY);
++              sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
++              //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY);
++              sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
++              //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY);
++              sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
++              //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY);
++              sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
++              //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY);
++              sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
++              //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY);
++              sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
++              //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY);
++              /* Disable sleep transitions */
++              sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
++      }
+ 
+       /* L4PER clocks */
+       sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2);
+@@ -723,50 +725,57 @@ static void enable_all_clocks(void)
+       sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2);
+       wait_on_value(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL, LDELAY);
+ 
+-      /* Enable Camera clocks */
+-      sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
+-      sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
+-      //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY);
+-      sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
+-      //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY);
+-      sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
+-
+-      /* Enable DSS clocks */
+-      /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
+-      *(volatile int*)0x4A307100 = 0x7; //DSS_PRM
+-      sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
+-      sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
+-      //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY);
+-      sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
+-      //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY);
+-      /* Check for DSS Clocks */
+-      while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00)
+-      /* Set HW_AUTO transition mode */
+-      sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
+-
+-      /* Enable SGX clocks */
+-      sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
+-      sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
+-      //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY);
+-      /* Check for SGX FCLK and ICLK */
+-      while ( (*(volatile int*)0x4A009200) != 0x302 );
+-      //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0);
+-      /* Enable hsi/unipro/usb clocks */
+-      sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
+-      //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY);
+-      sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
+-      //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY);
+-      sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
+-      //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY);
+-      sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
+-      //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY);
+-      sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
+-      //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY);
+-      sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
+-      //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY);
+-      /* enable the 32K, 48M optional clocks and enable the module */
++      if (omap_revision() == OMAP4430_ES1_0) {
++              /* Enable Camera clocks */
++              sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
++              sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
++              //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY);
++              sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
++              //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY);
++              sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
++
++              /* Enable DSS clocks */
++              /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
++              *(volatile int*)0x4A307100 = 0x7; //DSS_PRM
++              sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
++              sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
++              //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY);
++              sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
++              //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY);
++              /* Check for DSS Clocks */
++              while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00)
++              /* Set HW_AUTO transition mode */
++              sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
++
++              /* Enable SGX clocks */
++              sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
++              sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
++              //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY);
++              /* Check for SGX FCLK and ICLK */
++              while ( (*(volatile int*)0x4A009200) != 0x302 );
++              //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0);
++              /* Enable hsi/unipro/usb clocks */
++              sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
++              //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY);
++              sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
++              //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY);
++              sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
++              //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY);
++              sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
++              //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY);
++              sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
++              //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY);
++              sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
++              //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY);
++              /* enable the 32K, 48M optional clocks and enable the module */
++              sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
++              //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
++      }
++
++      /* Enable clocks for USB fast boot to work */
+       sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
+-      //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
++      sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
++
+       return;
+ }
+ 
+-- 
+1.6.6.1
+

diff --git a/recipes/x-load/x-load-git/0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch b/recipes/x-load/x-load-git/0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch
new file mode 100644 (file)
index 0000000..ffcf859
--- /dev/null
+++ b/recipes/x-load/x-load-git/0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch
@@ -0,0 +1,32 @@
+From fff093ab92c5dadd646130c38097dc167d2d0e1e Mon Sep 17 00:00:00 2001
+From: Rajeev Kulkarni <rajeevk@ti.com>
+Date: Tue, 26 Oct 2010 07:34:43 -0500
+Subject: [PATCH 2/5] OMAP4: Select DPLL PER Clock as source for SGX FCLK
+
+The correct frequncy for SGX is 307.2 Mhz.. If DPLL_PER
+is set 1536 Mhz, There is no need to change dividers, just
+parent clock need to change. And DPLL PER is set at 1536.
+
+Signed-off-by: Rajeev Kulkarni <rajeevk@ti.com>
+Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
+---
+ board/omap4430panda/clock.c |    3 +++
+ 1 files changed, 3 insertions(+), 0 deletions(-)
+
+diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
+index 149fc85..0961f51 100644
+--- a/board/omap4430panda/clock.c
++++ b/board/omap4430panda/clock.c
+@@ -772,6 +772,9 @@ static void enable_all_clocks(void)
+               //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
+       }
+ 
++      /* Select DPLL PER CLOCK as source for SGX FCLK */
++      sr32(CM_SGX_SGX_CLKCTRL, 24, 1, 0x1);
++
+       /* Enable clocks for USB fast boot to work */
+       sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
+       sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
+-- 
+1.6.6.1
+

diff --git a/recipes/x-load/x-load-git/0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch b/recipes/x-load/x-load-git/0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch
new file mode 100644 (file)
index 0000000..1475308
--- /dev/null
+++ b/recipes/x-load/x-load-git/0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch
@@ -0,0 +1,33 @@
+From daaaf036f3336e01a83a13dd93b8030b00a0af50 Mon Sep 17 00:00:00 2001
+From: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
+Date: Tue, 21 Dec 2010 12:03:50 -0200
+Subject: [PATCH 3/5] MUX: Configure SYS_NIRQ2 pin in safe mode
+
+SYS_NIRQ2 pin if not in safe mode, with audio driver
+enabled gates CORE RET. Hence configured in safe mode.
+Audio driver is expected to re-init the pin in the
+kernel.
+
+Patch from sdp, by Rajendra Nayak <rnayak@ti.com>
+
+Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
+---
+ board/omap4430panda/omap4430panda.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/board/omap4430panda/omap4430panda.c b/board/omap4430panda/omap4430panda.c
+index 5695733..814b2cb 100644
+--- a/board/omap4430panda/omap4430panda.c
++++ b/board/omap4430panda/omap4430panda.c
+@@ -910,7 +910,7 @@ int dram_init(void)
+       MV(CP(FREF_CLK1_OUT) , ( M0))  /* fref_clk1_out */ \
+       MV(CP(FREF_CLK2_OUT) , ( PTD | IEN | M3))  /* gpio_182 */ \
+       MV(CP(SYS_NIRQ1) , ( PTU | IEN | M0))  /* sys_nirq1 */ \
+-      MV(CP(SYS_NIRQ2) , ( PTU | IEN | M0))  /* sys_nirq2 */ \
++      MV(CP(SYS_NIRQ2) , (M7_SAFE))  /* sys_nirq2 */ \
+       MV(CP(SYS_BOOT0) , ( PTU | IEN | M3))  /* gpio_184 */ \
+       MV(CP(SYS_BOOT1) , ( M3))  /* gpio_185 */ \
+       MV(CP(SYS_BOOT2) , ( PTD | IEN | M3))  /* gpio_186 */ \
+-- 
+1.6.6.1
+

diff --git a/recipes/x-load/x-load-git/0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch b/recipes/x-load/x-load-git/0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch
new file mode 100644 (file)
index 0000000..9b6e2f9
--- /dev/null
+++ b/recipes/x-load/x-load-git/0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch
@@ -0,0 +1,34 @@
+From 4af562525c7779cd41ae9a68d56771407df558d7 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Mon, 4 Oct 2010 18:49:18 +0530
+Subject: [PATCH 4/5] OMAP4: clocks: Disable slimbus and pad_clks
+
+The slimbus and pad_clks if left enabled in x-loader
+would gate abe power domain from transitioning to RET.
+
+These should be enabled by the audio driver (if present)
+in the kernel.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
+---
+ board/omap4430panda/clock.c |    3 ---
+ 1 files changed, 0 insertions(+), 3 deletions(-)
+
+diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
+index 0961f51..c591a9f 100644
+--- a/board/omap4430panda/clock.c
++++ b/board/omap4430panda/clock.c
+@@ -333,9 +333,6 @@ static void configure_abe_dpll(u32 clk_index)
+       /* Select sys_clk as ref clk for ABE dpll */
+       sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0);
+ 
+-      /* Enable slimbus and pad clocks */
+-      sr32(CM_CLKSEL_ABE, 0, 32, 0x500);
+-
+       /* Unlock the ABE dpll */
+       sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS);
+       wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY);
+-- 
+1.6.6.1
+

diff --git a/recipes/x-load/x-load-git/0005-omap4-Make-1GHz-as-default-MPU-clock.patch b/recipes/x-load/x-load-git/0005-omap4-Make-1GHz-as-default-MPU-clock.patch
new file mode 100644 (file)
index 0000000..7c23f60
--- /dev/null
+++ b/recipes/x-load/x-load-git/0005-omap4-Make-1GHz-as-default-MPU-clock.patch
@@ -0,0 +1,49 @@
+From ce1ae065d5eb875990f55ede0405e061e4d4b8d3 Mon Sep 17 00:00:00 2001
+From: Sebastien Jan <s-jan@ti.com>
+Date: Wed, 22 Dec 2010 13:53:18 +0100
+Subject: [PATCH 5/5] omap4: Make 1GHz as default MPU clock
+
+Signed-off-by: Aneesh V <aneesh@ti.com>
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Signed-off-by: Sebastien Jan <s-jan@ti.com>
+Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
+---
+ Makefile                        |    8 ++++++++
+ include/configs/omap4430panda.h |    1 -
+ 2 files changed, 8 insertions(+), 1 deletions(-)
+
+diff --git a/Makefile b/Makefile
+index d134fdc..1c4fdd5 100644
+--- a/Makefile
++++ b/Makefile
+@@ -170,6 +170,14 @@ omap3530beagle_config :    unconfig
+ #########################################################################
+ omap4430panda_config :    unconfig
+       @./mkconfig $(@:_config=) arm omap4 omap4430panda
++      @[ -n "$(findstring _MPU_600MHz,$@)" ] || \
++              { echo "#define CONFIG_MPU_1000 1"      >> $(obj)include/config.h; \
++                echo "MPU at 1GHz revision.."; \
++              }
++      @[ -z "$(findstring _MPU_600MHz,$@)" ] || \
++              { echo "#define CONFIG_MPU_600 1"       >> $(obj)include/config.h; \
++                echo "MPU at 600MHz revision.."; \
++              }
+ 
+ #########################################################################
+ 
+diff --git a/include/configs/omap4430panda.h b/include/configs/omap4430panda.h
+index 74e2f42..eae02ef 100644
+--- a/include/configs/omap4430panda.h
++++ b/include/configs/omap4430panda.h
+@@ -44,7 +44,6 @@
+  * On Phoenix board vlotage needs to be bumped up
+  * before scaling the MPU up
+  */
+-#define CONFIG_MPU_600                1
+ #define CORE_190MHZ           1
+ /* Enable the below macro if MMC boot support is required */
+ #define CONFIG_MMC               1
+-- 
+1.6.6.1
+

diff --git a/recipes/x-load/x-load_git.bb b/recipes/x-load/x-load_git.bb
index e6df1cd..844ddfc 100644 (file)
--- a/recipes/x-load/x-load_git.bb
+++ b/recipes/x-load/x-load_git.bb
@@ -2,26 +2,24 @@ require x-load.inc
 
 DEFAULT_PREFERENCE_omap3-pandora = "-1"
 
-FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/x-load-git/${MACHINE}"
+FILESPATHPKG_prepend = "x-load-git:x-load-git/${MACHINE}"
 
-SRCREV = "319b26586fafb86f919f514bcd175838aaab96b3"
-SRCREV_beagleboard = "1c9276af4d6a5b7014a7630a1abeddf3b3177563"
-
-PV = "1.42+${PR}+gitr${SRCREV}"
-PV_beagleboard = "1.44+${PR}+gitr${SRCREV}"
-PR ="r18"
+PV = "1.44+${PR}+gitr${SRCREV}"
+PR ="r19"
 PE = "1"
 
-SRC_URI = "git://gitorious.org/x-load-omap3/mainline.git;branch=master;protocol=git"
+SRCREV = "6f3a26101303051e0f91b6213735b68ce804e94e"
+SRC_URI = "git://gitorious.org/x-loader/x-loader.git;branch=master;protocol=git \
+           file://0001-OMAP4-clocks-Enable-only-required-clks.patch \
+           file://0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch \
+           file://0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch \
+           file://0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch \
+           file://0005-omap4-Make-1GHz-as-default-MPU-clock.patch \
+          "
 
-SRC_URI_append_beagleboard = " \
-                              file://name.patch \
-                              file://bb8547fcbc54ecc7a75f9ad45a31042a04d8a2ce.patch \
-                              file://xm-mem.patch \
-                              file://0001-Fix-reading-FAT32-root-dirs-that-span-1-cluster.patch \
-"
+XLOAD_MACHINE_beagleboard = "omap3530beagle_config"
 
-SRC_URI_append_omap3-touchbook = " \
+SRC_URI_omap3-touchbook = "   git://gitorious.org/x-load-omap3/mainline.git;branch=master;protocol=git \\
                               file://name.patch \
                               file://screen-off.patch \
                              "