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amd64_edac: cleanup f10_early_channel_count
authorBorislav Petkov <borislav.petkov@amd.com>
Fri, 16 Oct 2009 17:55:49 +0000 (19:55 +0200)
committerBorislav Petkov <borislav.petkov@amd.com>
Mon, 7 Dec 2009 18:14:29 +0000 (19:14 +0100)
Do not read DCLR[01] again since this is done in
amd64_read_mc_registers() earlier. There can be more than two physical
DIMMs present so clamp the channels value to max 2. Also, do not report
DCT data width - it is also done earlier.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>

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