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MIPS: TXx9: Cache fixup
author
Atsushi Nemoto
<anemo@mba.ocn.ne.jp>
Tue, 19 Aug 2008 13:55:09 +0000
(22:55 +0900)
committer
Ralf Baechle
<ralf@linux-mips.org>
Sat, 11 Oct 2008 15:18:42 +0000
(16:18 +0100)
TX39/TX49 can enable/disable I/D cache at runtime. Add kernel options
to control them. This is useful to debug some cache-related issues,
such as aliasing or I/D coherency. Also enable CWF bit for TX49 SoCs.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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git.openpandora.org / pandora-kernel.git / commitdiff