Add initial support for Renesas R-Car X5H R8A78000 Ironhide board.
This consists mainly of DTs, Makefile and Kconfig entries and board
specific configuration files.
The DTs will be gradually switched over to Linux DTs via OF_UPSTREAM
once Linux DTs become available upstream, as upstreaming progresses.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
r7s72100-genmai.dtb \
r7s72100-gr-peach.dtb
+dtb-$(CONFIG_RCAR_GEN5) += \
+ r8a78000-ironhide.dtb
+
+ifdef CONFIG_RCAR_GEN5
+DTC_FLAGS += -R 4 -p 0x1000
+endif
+
dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source extras for U-Boot for the Ironhide board
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include "r8a78000-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the Ironhide board
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a78000.dtsi"
+#include <dt-bindings/net/ti-dp83869.h>
+
+/ {
+ model = "Renesas Ironhide board based on r8a78000";
+ compatible = "renesas,ironhide", "renesas,r8a78000";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ mmc0 = &mmc0;
+ serial0 = &hscif0;
+ };
+
+ chosen {
+ stdout-path = "serial0:1843200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x0 0x80000000>;
+ };
+
+ memory@1080000000 {
+ device_type = "memory";
+ reg = <0x10 0x80000000 0x0 0x80000000>;
+ };
+
+ memory@1200000000 {
+ device_type = "memory";
+ reg = <0x12 0x00000000 0x1 0x00000000>;
+ };
+
+ memory@1400000000 {
+ device_type = "memory";
+ reg = <0x14 0x00000000 0x1 0x00000000>;
+ };
+
+ memory@1600000000 {
+ device_type = "memory";
+ reg = <0x16 0x00000000 0x1 0x00000000>;
+ };
+
+ memory@1800000000 {
+ device_type = "memory";
+ reg = <0x18 0x00000000 0x1 0x00000000>;
+ };
+
+ memory@1a00000000 {
+ device_type = "memory";
+ reg = <0x1a 0x00000000 0x1 0x00000000>;
+ };
+
+ memory@1c00000000 {
+ device_type = "memory";
+ reg = <0x1c 0x00000000 0x1 0x00000000>;
+ };
+
+ memory@1e00000000 {
+ device_type = "memory";
+ reg = <0x1e 0x00000000 0x1 0x00000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <16666600>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&hscif0 {
+ pinctrl-0 = <&hscif0_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ clock-frequency = <400000>;
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "rohm,br24g01", "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <8>;
+ };
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+ð_pcs {
+ phys = <&mp_phy 2 1>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-1 = <&mmc0_pins>;
+ pinctrl-names = "default", "state_uhs";
+
+ bus-width = <8>;
+ full-pwr-cycle-in-suspend;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+
+ status = "okay";
+};
+
+&ufs0 {
+ status = "okay";
+};
+
+&ufs1 {
+ status = "okay";
+};
+
+&mp_phy {
+ status = "okay";
+};
+
+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ eth25g2_pins: eth25g2 {
+ groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint";
+ function = "eth25g2";
+ drive-strength = <24>;
+ };
+
+ ethes0_pins: ethes0 {
+ groups = "ethes0_match", "ethes0_capture", "ethes0_pps";
+ function = "ethes0";
+ drive-strength = <24>;
+ };
+
+ hscif0_pins: hscif0 {
+ groups = "hscif0_data", "hscif0_ctrl";
+ function = "hscif0";
+ };
+
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
+ i2c1_pins: i2c1 {
+ groups = "i2c1";
+ function = "i2c1";
+ };
+
+ mmc0_pins: mmc0 {
+ groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds";
+ function = "mmc0";
+ drive-strength = <24>;
+ };
+
+ rsw3_pins: rsw3 {
+ groups = "rsw3_match", "rsw3_capture", "rsw3_pps";
+ function = "rsw3";
+ drive-strength = <24>;
+ };
+
+ scif_clk_pins: scif-clk {
+ groups = "scif_clk";
+ function = "scif_clk";
+ };
+};
+
+&rswitch3 {
+ pinctrl-0 = <&rsw3_pins>, <ð25g2_pins>, <ðes0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*
+ * NOTE: Only port@4 is configured for R-Car X5H board.
+ * Other ports (0-3, 5-12) are currently unused or not
+ * connected.
+ */
+ port@4 {
+ reg = <4>;
+ renesas,connect_to_xpcs;
+ phy-handle = <&dp83869_phy>;
+ phy-mode = "sgmii";
+ phys = <ð_pcs 5>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dp83869_phy: ethernet-phy@2 {
+ reg = <2>;
+ ti,sgmii-interface;
+ ti,max-output-impedance;
+ ti,refclk-output-enable;
+ ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
+ };
+ };
+ };
+ };
+};
+
+&scif_clk {
+ clock-frequency = <26000000>;
+};
endmenu
+choice
+ prompt "Renesas ARM64 SoCs board select"
+ optional
+
+config TARGET_IRONHIDE
+ bool "Ironhide board"
+ imply R8A78000
+ help
+ Support for Renesas R-Car Gen5 Ironhide platform
+
+endchoice
+
+source "board/renesas/ironhide/Kconfig"
+
endif
obj-y += gen4-common.o
endif
endif
+
+ifdef CONFIG_RCAR_GEN5
+obj-y += gen5-common.o
+endif
endif
endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include <asm/arch/renesas.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <linux/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void init_generic_timer(void)
+{
+ const u32 freq = CONFIG_SYS_CLK_FREQ;
+
+ /* Update memory mapped and register based freqency */
+ asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
+ writel(freq, CNTFID0);
+
+ /* Enable counter */
+ setbits_le32(CNTCR_BASE, CNTCR_EN);
+}
+
+static void init_gic_v3(void)
+{
+ /* GIC v3 power on */
+ writel(BIT(1), GICR_LPI_PWRR);
+
+ /* Wait till the WAKER_CA_BIT changes to 0 */
+ clrbits_le32(GICR_LPI_WAKER, BIT(1));
+ while (readl(GICR_LPI_WAKER) & BIT(2))
+ ;
+
+ writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
+}
+
+void s_init(void)
+{
+ if (current_el() == 3)
+ init_generic_timer();
+}
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Allow WDT reset */
+ writel(RST_KCPROT_DIS, RST_RESKCPROT0);
+ clrbits_le32(RST_WDTRSTCR, RST_WWDT_RSTMSK | RST_RWDT_RSTMSK);
+
+ if (current_el() != 3)
+ return 0;
+ init_gic_v3();
+
+ return 0;
+}
+
+void __weak reset_cpu(void)
+{
+ writel(RST_KCPROT_DIS, RST_RESKCPROT0);
+ writel(0x1, RST_SWSRES1A);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ return 0;
+}
--- /dev/null
+if TARGET_IRONHIDE
+
+config SYS_SOC
+ default "renesas"
+
+config SYS_BOARD
+ default "ironhide"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "ironhide"
+
+endif
--- /dev/null
+#include <configs/renesas_rcar5.config>
+
+CONFIG_ARM=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_GEN5=y
+CONFIG_TARGET_IRONHIDE=y
+
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_ARMV8_PSCI=y
+CONFIG_ARM_SMCCC=y
+CONFIG_BAUDRATE=1843200
+CONFIG_BOOTCOMMAND="setexpr dloadaddr ${loadaddr} + 0x200000 && setexpr dloadaddr ${dloadaddr} \\\\& 0xffc00000 && setexpr kloadaddr ${dloadaddr} + 0x200000 && tftp ${dloadaddr} r8a78000-ironhide.dtb && tftp ${kloadaddr} Image && booti ${kloadaddr} - ${dloadaddr}"
+CONFIG_DEFAULT_DEVICE_TREE="r8a78000-ironhide"
+CONFIG_CLK_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_SCMI=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SCMI=y
+CONFIG_CMD_UFS=y
+CONFIG_DM_MAILBOX=y
+CONFIG_DM_RESET=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_MMC_DEVICE_INDEX=0
+CONFIG_ENV_MMC_EMMC_HW_PARTITION=2
+CONFIG_ENV_OFFSET=0xFFFE0000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_FIRMWARE=y
+CONFIG_NR_DRAM_BANKS=16
+CONFIG_POWER_DOMAIN=y
+CONFIG_RCAR_MFIS_MBOX=y
+CONFIG_RESET_SCMI=y
+CONFIG_SCMI_AGENT_MAILBOX=y
+CONFIG_SCMI_FIRMWARE=y
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_SCSI=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_SYS_BARGSIZE=2048
+CONFIG_SYS_BOOT_GET_CMDLINE=y
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_CLK_FREQ=1066666667
+CONFIG_UFS=y
+CONFIG_UFS_RENESAS_GEN5=y
--- /dev/null
+#include <configs/renesas_rcar64.config>
+
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_LOAD_ADDR=0x9E600000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+
+CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_CMD_MMC=y
+CONFIG_DM_ETH_PHY=y
+# CONFIG_MMC_HS200_SUPPORT is not set
+# CONFIG_MMC_IO_VOLTAGE is not set
+# CONFIG_MMC_UHS_SUPPORT is not set
+CONFIG_PHY_R8A78000_ETHERNET_PCS=y
+CONFIG_PHY_R8A78000_MP_PHY=y
+CONFIG_PHY_TI_DP83869=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_RENESAS_ETHER_SWITCH=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SYS_I2C_RCAR_I2C=y
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __IRONHIDE_H
+#define __IRONHIDE_H
+
+#include "rcar-gen5-common.h"
+
+#endif /* __IRONHIDE_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2025 Renesas Electronics Corporation
+ */
+
+#ifndef __RCAR_GEN5_COMMON_H
+#define __RCAR_GEN5_COMMON_H
+
+#include <asm/arch/renesas.h>
+
+/* Console */
+#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200, 3250000 }
+
+/* Memory */
+#define DRAM_RSV_SIZE 0x08000000
+#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
+#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
+#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
+
+/* Environment setting */
+#define CFG_EXTRA_ENV_SETTINGS \
+ "bootm_size=0x10000000\0"
+
+#endif /* __RCAR_GEN5_COMMON_H */
git.openpandora.org / pandora-u-boot.git / commitdiff