cxgb4/cxgb4vf: For T5 use Packing and Padding Boundaries for SGE DMA transfers

T5 introduces the ability to have separate Packing and Padding Boundaries
for SGE DMA transfers from the chip to Host Memory. This change set takes
advantage of that to set up a smaller Padding Boundary to conserve PCI Link
and Memory Bandwidth with T5.

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --cc drivers/net/ethernet/chelsio/cxgb4/sge.c
Simple merge

diff --cc drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
Simple merge

diff --cc drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
Simple merge

diff --cc drivers/net/ethernet/chelsio/cxgb4vf/sge.c
Simple merge

diff --cc drivers/net/ethernet/chelsio/cxgb4vf/t4vf_common.h
Simple merge

diff --cc drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
Simple merge