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tg3: Allow DMAs to cross cacheline boundaries
authorMatt Carlson <mcarlson@broadcom.com>
Fri, 13 Nov 2009 13:03:40 +0000 (13:03 +0000)
committerDavid S. Miller <davem@davemloft.net>
Mon, 16 Nov 2009 06:14:43 +0000 (22:14 -0800)
By default, the 5717 (and future chips) break up PCIe DMA packets across
cacheline boundaries.  This isn't necessary on x86.  This patch
selectively loosens the restriction.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

No differences found
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