Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u...

Xilinx changes for v2021.04-rc3

qspi:
- Support for dual/quad mode
- Fix speed handling

clk:
- Add clock enable function for zynq/zynqmp/versal

gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path

fpga:
- Fix buffer alignment for ZynqMP

xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name

diff --cc board/xilinx/common/board.c
Simple merge

diff --cc board/xilinx/zynq/board.c
Simple merge

diff --cc board/xilinx/zynqmp/zynqmp.c
Simple merge

diff --cc drivers/clk/clk_zynq.c
Simple merge

diff --cc drivers/spi/zynq_qspi.c
Simple merge

diff --cc drivers/spi/zynq_spi.c
Simple merge

diff --cc drivers/spi/zynqmp_gqspi.c
Simple merge