arm64: renesas: Deduplicate R-Car Gen4 board files
authorMarek Vasut <marek.vasut+renesas@mailbox.org>
Thu, 12 Dec 2024 13:37:34 +0000 (14:37 +0100)
committerMarek Vasut <marek.vasut+renesas@mailbox.org>
Sun, 29 Dec 2024 15:55:31 +0000 (16:55 +0100)
All R-Car Gen4 board files are copies of one another at this point.
Deduplicate them into single board/renesas/rcar-common/gen4-common.c
and remove all the duplicates. The one exception is R-Car V3U Falcon
board, which enables RWDT reset in board_init(), conditionally build
RWDT enablement in board_init() in the new common code for V3U.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
board/renesas/falcon/Makefile
board/renesas/falcon/falcon.c [deleted file]
board/renesas/grayhawk/Makefile
board/renesas/rcar-common/gen4-common.c [moved from board/renesas/grayhawk/grayhawk.c with 71% similarity]
board/renesas/spider/Makefile
board/renesas/spider/spider.c [deleted file]
board/renesas/whitehawk/Makefile
board/renesas/whitehawk/whitehawk.c [deleted file]

index 2e240d3..48fcfac 100644 (file)
@@ -9,5 +9,5 @@
 ifdef CONFIG_XPL_BUILD
 obj-y  := ../rcar-common/gen3-spl.o
 else
-obj-y  := falcon.o ../rcar-common/common.o
+obj-y  := ../rcar-common/gen4-common.o ../rcar-common/common.o
 endif
diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c
deleted file mode 100644 (file)
index c88257d..0000000
+++ /dev/null
@@ -1,102 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board/renesas/falcon/falcon.c
- *     This file is Falcon board support.
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-
-#include <asm/arch/renesas.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/processor.h>
-#include <linux/errno.h>
-#include <asm/system.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define CPGWPR         0xE6150000
-#define CPGWPCR                0xE6150004
-
-#define EXTAL_CLK      16666600u
-#define CNTCR_BASE     0xE6080000
-#define CNTFID0                (CNTCR_BASE + 0x020)
-#define CNTCR_EN       BIT(0)
-
-static void init_generic_timer(void)
-{
-       u32 freq;
-
-       /* Set frequency data in CNTFID0 */
-       freq = EXTAL_CLK;
-
-       /* Update memory mapped and register based freqency */
-       asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
-       writel(freq, CNTFID0);
-
-       /* Enable counter */
-       setbits_le32(CNTCR_BASE, CNTCR_EN);
-}
-
-/* Distributor Registers */
-#define GICD_BASE      0xF1000000
-
-/* ReDistributor Registers for Control and Physical LPIs */
-#define GICR_LPI_BASE  0xF1060000
-#define GICR_WAKER     0x0014
-#define GICR_PWRR      0x0024
-#define GICR_LPI_WAKER (GICR_LPI_BASE + GICR_WAKER)
-#define GICR_LPI_PWRR  (GICR_LPI_BASE + GICR_PWRR)
-
-/* ReDistributor Registers for SGIs and PPIs */
-#define GICR_SGI_BASE  0xF1070000
-#define GICR_IGROUPR0  0x0080
-
-static void init_gic_v3(void)
-{
-        /* GIC v3 power on */
-       writel(0x00000002, (GICR_LPI_PWRR));
-
-       /* Wait till the WAKER_CA_BIT changes to 0 */
-       writel(readl(GICR_LPI_WAKER) & ~0x00000002, (GICR_LPI_WAKER));
-       while (readl(GICR_LPI_WAKER) & 0x00000004)
-               ;
-
-       writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
-}
-
-void s_init(void)
-{
-       if (current_el() == 3)
-               init_generic_timer();
-}
-
-int board_early_init_f(void)
-{
-       /* Unlock CPG access */
-       writel(0x5A5AFFFF, CPGWPR);
-       writel(0xA5A50000, CPGWPCR);
-
-       return 0;
-}
-
-#define RST_BASE       0xE6160000 /* Domain0 */
-#define RST_WDTRSTCR   (RST_BASE + 0x10)
-#define RST_RWDT       0xA55A8002
-
-int board_init(void)
-{
-       /* address of boot parameters */
-       gd->bd->bi_boot_params = CONFIG_TEXT_BASE + 0x50000;
-
-       if (current_el() == 3) {
-               init_gic_v3();
-
-               /* Enable RWDT reset */
-               writel(RST_RWDT, RST_WDTRSTCR);
-       }
-
-       return 0;
-}
index 9c5b8c9..7414b77 100644 (file)
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  := grayhawk.o ../rcar-common/common.o
+obj-y  := ../rcar-common/gen4-common.o ../rcar-common/common.o
similarity index 71%
rename from board/renesas/grayhawk/grayhawk.c
rename to board/renesas/rcar-common/gen4-common.c
index 6c8fca8..36a51bc 100644 (file)
@@ -1,9 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * board/renesas/grayhawk/grayhawk.c
- *     This file is Gray Hawk board support.
+ * board/renesas/rcar-common/gen4-common.c
  *
- * Copyright (C) 2023 Renesas Electronics Corp.
+ * Copyright (C) 2021-2024 Renesas Electronics Corp.
  */
 
 #include <asm/arch/renesas.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/processor.h>
-#include <linux/errno.h>
 #include <asm/system.h>
+#include <linux/errno.h>
+
+#define RST_BASE       0xE6160000 /* Domain0 */
+#define RST_WDTRSTCR   (RST_BASE + 0x10)
+#define RST_RWDT       0xA55A8002
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -59,8 +62,15 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-       if (current_el() == 3)
-               init_gic_v3();
+       if (current_el() != 3)
+               return 0;
+       init_gic_v3();
+
+       /* Enable RWDT reset on V3U in EL3 */
+       if (IS_ENABLED(CONFIG_R8A779A0) &&
+           renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779A0) {
+               writel(RST_RWDT, RST_WDTRSTCR);
+       }
 
        return 0;
 }
index 545cb58..9489917 100644 (file)
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  := spider.o ../rcar-common/common.o
+obj-y  := ../rcar-common/gen4-common.o ../rcar-common/common.o
diff --git a/board/renesas/spider/spider.c b/board/renesas/spider/spider.c
deleted file mode 100644 (file)
index 414948f..0000000
+++ /dev/null
@@ -1,66 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board/renesas/spider/spider.c
- *     This file is Spider board support.
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-#include <asm/arch/renesas.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/processor.h>
-#include <asm/system.h>
-#include <linux/errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void init_generic_timer(void)
-{
-       const u32 freq = CONFIG_SYS_CLK_FREQ;
-
-       /* Update memory mapped and register based freqency */
-       asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
-       writel(freq, CNTFID0);
-
-       /* Enable counter */
-       setbits_le32(CNTCR_BASE, CNTCR_EN);
-}
-
-static void init_gic_v3(void)
-{
-        /* GIC v3 power on */
-       writel(BIT(1), GICR_LPI_PWRR);
-
-       /* Wait till the WAKER_CA_BIT changes to 0 */
-       clrbits_le32(GICR_LPI_WAKER, BIT(1));
-       while (readl(GICR_LPI_WAKER) & BIT(2))
-               ;
-
-       writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
-}
-
-void s_init(void)
-{
-       if (current_el() == 3)
-               init_generic_timer();
-}
-
-int board_early_init_f(void)
-{
-       /* Unlock CPG access */
-       writel(0x5A5AFFFF, CPGWPR);
-       writel(0xA5A50000, CPGWPCR);
-
-       return 0;
-}
-
-int board_init(void)
-{
-       if (current_el() == 3)
-               init_gic_v3();
-
-       return 0;
-}
index ed5bdc0..38726cd 100644 (file)
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  := whitehawk.o ../rcar-common/common.o
+obj-y  := ../rcar-common/gen4-common.o ../rcar-common/common.o
diff --git a/board/renesas/whitehawk/whitehawk.c b/board/renesas/whitehawk/whitehawk.c
deleted file mode 100644 (file)
index 3a10b02..0000000
+++ /dev/null
@@ -1,66 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board/renesas/whitehawk/whitehawk.c
- *     This file is White Hawk board support.
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-#include <asm/arch/renesas.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/processor.h>
-#include <linux/errno.h>
-#include <asm/system.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void init_generic_timer(void)
-{
-       const u32 freq = CONFIG_SYS_CLK_FREQ;
-
-       /* Update memory mapped and register based freqency */
-       asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
-       writel(freq, CNTFID0);
-
-       /* Enable counter */
-       setbits_le32(CNTCR_BASE, CNTCR_EN);
-}
-
-static void init_gic_v3(void)
-{
-       /* GIC v3 power on */
-       writel(BIT(1), GICR_LPI_PWRR);
-
-       /* Wait till the WAKER_CA_BIT changes to 0 */
-       clrbits_le32(GICR_LPI_WAKER, BIT(1));
-       while (readl(GICR_LPI_WAKER) & BIT(2))
-               ;
-
-       writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
-}
-
-void s_init(void)
-{
-       if (current_el() == 3)
-               init_generic_timer();
-}
-
-int board_early_init_f(void)
-{
-       /* Unlock CPG access */
-       writel(0x5A5AFFFF, CPGWPR);
-       writel(0xA5A50000, CPGWPCR);
-
-       return 0;
-}
-
-int board_init(void)
-{
-       if (current_el() == 3)
-               init_gic_v3();
-
-       return 0;
-}