arm: socfpga: Disable GIC for Agilex5

Status polling is used instead of using interrupt controller for Agilex5.

Disabling GICV3 in Agilex5 target, as well as disabling GICV2 enabled by
default for all SoCFPGA devices.

All the other SoCFPGA devices uses GICV2, thus enabling GICV2 in each of
the devices.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index da6f117..c0a6a07 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1128,7 +1128,6 @@ config ARCH_SOCFPGA
        select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
        select DM
        select DM_SERIAL
-       select GICV2
        select GPIO_EXTRA_HEADER
        select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
        select OF_CONTROL

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 6b6a162..a76a9fb 100644 (file)
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -55,6 +55,7 @@ config TARGET_SOCFPGA_AGILEX
        select BINMAN if SPL_ATF
        select CLK
        select FPGA_INTEL_SDM_MAILBOX
+       select GICV2
        select NCORE_CACHE
        select SPL_CLK if SPL
        select TARGET_SOCFPGA_SOC64
@@ -64,7 +65,6 @@ config TARGET_SOCFPGA_AGILEX5
        select BINMAN if SPL_ATF
        select CLK
        select FPGA_INTEL_SDM_MAILBOX
-       select GICV3
        select SPL_CLK if SPL
        select TARGET_SOCFPGA_SOC64
 
@@ -74,6 +74,7 @@ config TARGET_SOCFPGA_ARRIA5
 
 config TARGET_SOCFPGA_ARRIA10
        bool
+       select GICV2
        select SPL_ALTERA_SDRAM
        select SPL_BOARD_INIT if SPL
        select SPL_CACHE if SPL
@@ -118,6 +119,7 @@ config TARGET_SOCFPGA_N5X
        select ARMV8_SET_SMPEN
        select BINMAN if SPL_ATF
        select CLK
+       select GICV2
        select FPGA_INTEL_SDM_MAILBOX
        select NCORE_CACHE
        select SPL_ALTERA_SDRAM
@@ -137,6 +139,7 @@ config TARGET_SOCFPGA_STRATIX10
        select ARMV8_SET_SMPEN
        select BINMAN if SPL_ATF
        select FPGA_INTEL_SDM_MAILBOX
+       select GICV2
        select TARGET_SOCFPGA_SOC64
 
 choice