drm/i915: Add some L3 registers to the parser whitelist

Beignet needs these in order to program the L3 cache config for
OpenCL workloads, particularly when using SLM.

Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --cc drivers/gpu/drm/i915/i915_cmd_parser.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_reg.h
Simple merge