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ath9k_hw: change the way we initialize the pll for ar9271
authorLuis R. Rodriguez <lrodriguez@atheros.com>
Mon, 19 Oct 2009 06:33:34 +0000 (02:33 -0400)
committerJohn W. Linville <linville@tuxdriver.com>
Fri, 30 Oct 2009 20:50:36 +0000 (16:50 -0400)
We adjust the core clock for ar9271 to 117 MHz; this also
requires us to adjust the baud divider based on the targetted
baud rate.

Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

No differences found
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