powerpc/fsl: Force coherent memory on e500mc derivatives

In CoreNet systems it is not allowed to mix M and non-M mappings to the
same memory, and coherent DMA accesses are considered to be M mappings
for this purpose.  Ignoring this has been observed to cause hard
lockups in non-SMP kernels on e6500.

Furthermore, e6500 implements the LRAT (logical to real address table)
which allows KVM guests to control the WIMGE bits.  This means that
KVM cannot force the M bit on the way it usually does, so the guest had
better set it itself.

Signed-off-by: Scott Wood <scottwood@freescale.com>

diff --cc arch/powerpc/include/asm/pte-common.h
Simple merge

diff --cc arch/powerpc/kernel/exceptions-64e.S
Simple merge

diff --cc arch/powerpc/kernel/fsl_booke_entry_mapping.S
Simple merge

diff --cc arch/powerpc/mm/fsl_booke_mmu.c
Simple merge