OMAP3630: PM: Disable L2 cache while invalidating L2 cache

While coming out of MPU OSWR/OFF states, L2 controller is reseted.
The reset behavior is implementation specific as per ARMv7 TRM and
hence $L2 needs to be invalidated before it's use. Since the
AUXCTRL register is also reconfigured, disable L2 cache before
invalidating it and re-enables it afterwards. This is as per
Cortex-A8 ARM documentation.
Currently this is identified as being needed on OMAP3630 as the
disable/enable is done from "public side" while, on OMAP3430, this
is done in the "secure side".

Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tony Lindgren <tony@atomide.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>

diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 8d9aa3e..5e0bee9 100644 (file)
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -90,8 +90,10 @@ extern unsigned int omap34xx_cpu_suspend_sz;
 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
 extern u16 pm34xx_errata;
 #define IS_PM34XX_ERRATUM(id)          (pm34xx_errata & (id))
+extern void enable_omap3630_toggle_l2_on_restore(void);
 #else
 #define IS_PM34XX_ERRATUM(id)          0
+static inline void enable_omap3630_toggle_l2_on_restore(void) { }
 #endif         /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
 
 #endif

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7dbc000..96e309d 100644 (file)
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -996,8 +996,11 @@ void omap_push_sram_idle(void)
 
 static void __init pm_errata_configure(void)
 {
-       if (cpu_is_omap3630())
+       if (cpu_is_omap3630()) {
                pm34xx_errata |= PM_RTA_ERRATUM_i608;
+               /* Enable the l2 cache toggling in sleep logic */
+               enable_omap3630_toggle_l2_on_restore();
+       }
 }
 
 static int __init omap3_pm_init(void)

diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 4abf447..50887c7 100644 (file)
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -110,6 +110,19 @@ ENTRY(get_omap3630_restore_pointer)
 ENTRY(get_omap3630_restore_pointer_sz)
         .word   . - get_omap3630_restore_pointer
 
+       .text
+/*
+ * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
+ * This function sets up a fflag that will allow for this toggling to take
+ * place on 3630. Hopefully some version in the future maynot need this
+ */
+ENTRY(enable_omap3630_toggle_l2_on_restore)
+        stmfd   sp!, {lr}     @ save registers on stack
+       /* Setup so that we will disable and enable l2 */
+       mov     r1, #0x1
+       str     r1, l2dis_3630
+        ldmfd   sp!, {pc}     @ restore regs and return
+
        .text
 /* Function call to get the restore pointer for for ES3 to resume from OFF */
 ENTRY(get_es3_restore_pointer)
@@ -283,6 +296,14 @@ restore:
         moveq   r9, #0x3        @ MPU OFF => L1 and L2 lost
        movne   r9, #0x1        @ Only L1 and L2 lost => avoid L2 invalidation
        bne     logic_l1_restore
+
+       ldr     r0, l2dis_3630
+       cmp     r0, #0x1        @ should we disable L2 on 3630?
+       bne     skipl2dis
+       mrc     p15, 0, r0, c1, c0, 1
+       bic     r0, r0, #2      @ disable L2 cache
+       mcr     p15, 0, r0, c1, c0, 1
+skipl2dis:
        ldr     r0, control_stat
        ldr     r1, [r0]
        and     r1, #0x700
@@ -343,6 +364,13 @@ smi:    .word 0xE1600070           @ Call SMI monitor (smieq)
        mov     r12, #0x2
        .word 0xE1600070        @ Call SMI monitor (smieq)
 logic_l1_restore:
+       ldr     r1, l2dis_3630
+       cmp     r1, #0x1        @ Do we need to re-enable L2 on 3630?
+       bne     skipl2reen
+       mrc     p15, 0, r1, c1, c0, 1
+       orr     r1, r1, #2      @ re-enable L2 cache
+       mcr     p15, 0, r1, c1, c0, 1
+skipl2reen:
        mov     r1, #0
        /* Invalidate all instruction caches to PoU
         * and flush branch target cache */
@@ -679,6 +707,8 @@ control_mem_rta:
        .word   CONTROL_MEM_RTA_CTRL
 kernel_flush:
        .word v7_flush_dcache_all
+l2dis_3630:
+       .word 0
        /*
         * When exporting to userspace while the counters are in SRAM,
         * these 2 words need to be at the end to facilitate retrival!