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drm/i915/skl: Program PLL for edp1.4 intermediate frequencies
authorSonika Jindal <sonika.jindal@intel.com>
Sat, 21 Feb 2015 05:42:13 +0000 (11:12 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 17 Mar 2015 21:29:57 +0000 (22:29 +0100)
v2: Making the link_clock half in switch inline with the DPLL_CTRL1_* macros
(Ville)

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_dp.c patch | blob | history

diff --cc drivers/gpu/drm/i915/intel_dp.c
Simple merge
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