mmc: fsl_esdhc_imx: Reset tuning logic

When supporting partition reset for SoC such as i.MX95 , the Linux
Kernel may have configured the tuning, while after force reset by
wdog or else, uboot CMD0 will never pass unless config RSTT to reset
tuning logic.

Since RSTA and RSTT are independent, so need both to be reseted in the
controller.

Acked-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index debfc78..fb41010 100644 (file)
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -987,11 +987,11 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
        ulong start;
 
        /* Reset the entire host controller */
-       esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
+       esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA | SYSCTL_RSTT);
 
        /* Wait until the controller is available */
        start = get_timer(0);
-       while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
+       while ((esdhc_read32(&regs->sysctl) & (SYSCTL_RSTA | SYSCTL_RSTT))) {
                if (get_timer(start) > 1000)
                        return -ETIMEDOUT;
        }
@@ -1095,11 +1095,11 @@ static int esdhc_reset(struct fsl_esdhc *regs)
        ulong start;
 
        /* reset the controller */
-       esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
+       esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA | SYSCTL_RSTT);
 
        /* hardware clears the bit when it is done */
        start = get_timer(0);
-       while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
+       while ((esdhc_read32(&regs->sysctl) & (SYSCTL_RSTA | SYSCTL_RSTT))) {
                if (get_timer(start) > 100) {
                        printf("MMC/SD: Reset never completed.\n");
                        return -ETIMEDOUT;

diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h
index b8efd2a..8612b56 100644 (file)
--- a/include/fsl_esdhc_imx.h
+++ b/include/fsl_esdhc_imx.h
@@ -31,6 +31,7 @@
 #define SYSCTL_RSTA            0x01000000
 #define SYSCTL_RSTC            0x02000000
 #define SYSCTL_RSTD            0x04000000
+#define SYSCTL_RSTT            0x10000000
 
 #define VENDORSPEC_CKEN                0x00004000
 #define VENDORSPEC_PEREN       0x00002000