#include <core/engine.h>
struct nvkm_gr {
- struct nvkm_engine base;
+ struct nvkm_engine engine;
/* Returns chipset-specific counts of units packed into an u64.
*/
#define nvkm_gr_create(p,e,c,y,d) \
nvkm_engine_create((p), (e), (c), (y), "PGRAPH", "graphics", (d))
#define nvkm_gr_destroy(d) \
- nvkm_engine_destroy(&(d)->base)
+ nvkm_engine_destroy(&(d)->engine)
#define nvkm_gr_init(d) \
- nvkm_engine_init(&(d)->base)
+ nvkm_engine_init(&(d)->engine)
#define nvkm_gr_fini(d,s) \
- nvkm_engine_fini(&(d)->base, (s))
+ nvkm_engine_fini(&(d)->engine, (s))
#define _nvkm_gr_dtor _nvkm_engine_dtor
#define _nvkm_gr_init _nvkm_engine_init
-nvkm-y += nvkm/engine/gr/ctxnv40.o
-nvkm-y += nvkm/engine/gr/ctxnv50.o
-nvkm-y += nvkm/engine/gr/ctxgf100.o
-nvkm-y += nvkm/engine/gr/ctxgf108.o
-nvkm-y += nvkm/engine/gr/ctxgf104.o
-nvkm-y += nvkm/engine/gr/ctxgf110.o
-nvkm-y += nvkm/engine/gr/ctxgf117.o
-nvkm-y += nvkm/engine/gr/ctxgf119.o
-nvkm-y += nvkm/engine/gr/ctxgk104.o
-nvkm-y += nvkm/engine/gr/ctxgk20a.o
-nvkm-y += nvkm/engine/gr/ctxgk110.o
-nvkm-y += nvkm/engine/gr/ctxgk110b.o
-nvkm-y += nvkm/engine/gr/ctxgk208.o
-nvkm-y += nvkm/engine/gr/ctxgm107.o
-nvkm-y += nvkm/engine/gr/ctxgm204.o
-nvkm-y += nvkm/engine/gr/ctxgm206.o
-nvkm-y += nvkm/engine/gr/ctxgm20b.o
nvkm-y += nvkm/engine/gr/nv04.o
nvkm-y += nvkm/engine/gr/nv10.o
nvkm-y += nvkm/engine/gr/nv20.o
nvkm-y += nvkm/engine/gr/gm204.o
nvkm-y += nvkm/engine/gr/gm206.o
nvkm-y += nvkm/engine/gr/gm20b.o
+
+nvkm-y += nvkm/engine/gr/ctxnv40.o
+nvkm-y += nvkm/engine/gr/ctxnv50.o
+nvkm-y += nvkm/engine/gr/ctxgf100.o
+nvkm-y += nvkm/engine/gr/ctxgf108.o
+nvkm-y += nvkm/engine/gr/ctxgf104.o
+nvkm-y += nvkm/engine/gr/ctxgf110.o
+nvkm-y += nvkm/engine/gr/ctxgf117.o
+nvkm-y += nvkm/engine/gr/ctxgf119.o
+nvkm-y += nvkm/engine/gr/ctxgk104.o
+nvkm-y += nvkm/engine/gr/ctxgk20a.o
+nvkm-y += nvkm/engine/gr/ctxgk110.o
+nvkm-y += nvkm/engine/gr/ctxgk110b.o
+nvkm-y += nvkm/engine/gr/ctxgk208.o
+nvkm-y += nvkm/engine/gr/ctxgm107.o
+nvkm-y += nvkm/engine/gr/ctxgm204.o
+nvkm-y += nvkm/engine/gr/ctxgm206.o
+nvkm-y += nvkm/engine/gr/ctxgm20b.o
return;
}
- nv_wr32(info->priv, addr, data);
+ nv_wr32(info->gr, addr, data);
}
void
gf100_grctx_generate_bundle(struct gf100_grctx *info)
{
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);
void
gf100_grctx_generate_pagepool(struct gf100_grctx *info)
{
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
void
gf100_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct gf100_gr_priv *priv = info->priv;
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv);
+ struct gf100_gr *gr = info->gr;
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(gr);
const u32 attrib = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
const u32 access = NV_MEM_ACCESS_RW;
const int s = 12;
- const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access);
+ const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access);
int gpc, tpc;
u32 bo = 0;
mmio_refn(info, 0x419848, 0x10000000, s, b);
mmio_wr32(info, 0x405830, (attrib << 16));
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
const u32 o = TPC_UNIT(gpc, tpc, 0x0520);
mmio_skip(info, o, (attrib << 16) | ++bo);
mmio_wr32(info, o, (attrib << 16) | --bo);
}
void
-gf100_grctx_generate_unkn(struct gf100_gr_priv *priv)
+gf100_grctx_generate_unkn(struct gf100_gr *gr)
{
}
void
-gf100_grctx_generate_tpcid(struct gf100_gr_priv *priv)
+gf100_grctx_generate_tpcid(struct gf100_gr *gr)
{
int gpc, tpc, id;
for (tpc = 0, id = 0; tpc < 4; tpc++) {
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- if (tpc < priv->tpc_nr[gpc]) {
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x4e8), id);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id);
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ if (tpc < gr->tpc_nr[gpc]) {
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x698), id);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x4e8), id);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x088), id);
id++;
}
- nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]);
}
}
}
void
-gf100_grctx_generate_r406028(struct gf100_gr_priv *priv)
+gf100_grctx_generate_r406028(struct gf100_gr *gr)
{
u32 tmp[GPC_MAX / 8] = {}, i = 0;
- for (i = 0; i < priv->gpc_nr; i++)
- tmp[i / 8] |= priv->tpc_nr[i] << ((i % 8) * 4);
+ for (i = 0; i < gr->gpc_nr; i++)
+ tmp[i / 8] |= gr->tpc_nr[i] << ((i % 8) * 4);
for (i = 0; i < 4; i++) {
- nv_wr32(priv, 0x406028 + (i * 4), tmp[i]);
- nv_wr32(priv, 0x405870 + (i * 4), tmp[i]);
+ nv_wr32(gr, 0x406028 + (i * 4), tmp[i]);
+ nv_wr32(gr, 0x405870 + (i * 4), tmp[i]);
}
}
void
-gf100_grctx_generate_r4060a8(struct gf100_gr_priv *priv)
+gf100_grctx_generate_r4060a8(struct gf100_gr *gr)
{
u8 tpcnr[GPC_MAX], data[TPC_MAX];
int gpc, tpc, i;
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
memset(data, 0x1f, sizeof(data));
gpc = -1;
- for (tpc = 0; tpc < priv->tpc_total; tpc++) {
+ for (tpc = 0; tpc < gr->tpc_total; tpc++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
tpcnr[gpc]--;
data[tpc] = gpc;
}
for (i = 0; i < 4; i++)
- nv_wr32(priv, 0x4060a8 + (i * 4), ((u32 *)data)[i]);
+ nv_wr32(gr, 0x4060a8 + (i * 4), ((u32 *)data)[i]);
}
void
-gf100_grctx_generate_r418bb8(struct gf100_gr_priv *priv)
+gf100_grctx_generate_r418bb8(struct gf100_gr *gr)
{
u32 data[6] = {}, data2[2] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, i;
/* calculate first set of magics */
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
gpc = -1;
- for (tpc = 0; tpc < priv->tpc_total; tpc++) {
+ for (tpc = 0; tpc < gr->tpc_total; tpc++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
tpcnr[gpc]--;
/* and the second... */
shift = 0;
- ntpcv = priv->tpc_total;
+ ntpcv = gr->tpc_total;
while (!(ntpcv & (1 << 4))) {
ntpcv <<= 1;
shift++;
data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
/* GPC_BROADCAST */
- nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) |
- priv->magic_not_rop_nr);
+ nv_wr32(gr, 0x418bb8, (gr->tpc_total << 8) |
+ gr->magic_not_rop_nr);
for (i = 0; i < 6; i++)
- nv_wr32(priv, 0x418b08 + (i * 4), data[i]);
+ nv_wr32(gr, 0x418b08 + (i * 4), data[i]);
/* GPC_BROADCAST.TP_BROADCAST */
- nv_wr32(priv, 0x419bd0, (priv->tpc_total << 8) |
- priv->magic_not_rop_nr | data2[0]);
- nv_wr32(priv, 0x419be4, data2[1]);
+ nv_wr32(gr, 0x419bd0, (gr->tpc_total << 8) |
+ gr->magic_not_rop_nr | data2[0]);
+ nv_wr32(gr, 0x419be4, data2[1]);
for (i = 0; i < 6; i++)
- nv_wr32(priv, 0x419b00 + (i * 4), data[i]);
+ nv_wr32(gr, 0x419b00 + (i * 4), data[i]);
/* UNK78xx */
- nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) |
- priv->magic_not_rop_nr);
+ nv_wr32(gr, 0x4078bc, (gr->tpc_total << 8) |
+ gr->magic_not_rop_nr);
for (i = 0; i < 6; i++)
- nv_wr32(priv, 0x40780c + (i * 4), data[i]);
+ nv_wr32(gr, 0x40780c + (i * 4), data[i]);
}
void
-gf100_grctx_generate_r406800(struct gf100_gr_priv *priv)
+gf100_grctx_generate_r406800(struct gf100_gr *gr)
{
u64 tpc_mask = 0, tpc_set = 0;
u8 tpcnr[GPC_MAX];
int gpc, tpc;
int i, a, b;
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
- for (gpc = 0; gpc < priv->gpc_nr; gpc++)
- tpc_mask |= ((1ULL << priv->tpc_nr[gpc]) - 1) << (gpc * 8);
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++)
+ tpc_mask |= ((1ULL << gr->tpc_nr[gpc]) - 1) << (gpc * 8);
for (i = 0, gpc = -1, b = -1; i < 32; i++) {
- a = (i * (priv->tpc_total - 1)) / 32;
+ a = (i * (gr->tpc_total - 1)) / 32;
if (a != b) {
b = a;
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
+ tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
tpc_set |= 1ULL << ((gpc * 8) + tpc);
}
- nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
- nv_wr32(priv, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask));
- if (priv->gpc_nr > 4) {
- nv_wr32(priv, 0x406804 + (i * 0x20), upper_32_bits(tpc_set));
- nv_wr32(priv, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask));
+ nv_wr32(gr, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
+ nv_wr32(gr, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask));
+ if (gr->gpc_nr > 4) {
+ nv_wr32(gr, 0x406804 + (i * 0x20), upper_32_bits(tpc_set));
+ nv_wr32(gr, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask));
}
}
}
void
-gf100_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
- gf100_gr_mmio(priv, oclass->hub);
- gf100_gr_mmio(priv, oclass->gpc);
- gf100_gr_mmio(priv, oclass->zcull);
- gf100_gr_mmio(priv, oclass->tpc);
- gf100_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(gr, oclass->hub);
+ gf100_gr_mmio(gr, oclass->gpc);
+ gf100_gr_mmio(gr, oclass->zcull);
+ gf100_gr_mmio(gr, oclass->tpc);
+ gf100_gr_mmio(gr, oclass->ppc);
- nv_wr32(priv, 0x404154, 0x00000000);
+ nv_wr32(gr, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
oclass->attrib(info);
- oclass->unkn(priv);
-
- gf100_grctx_generate_tpcid(priv);
- gf100_grctx_generate_r406028(priv);
- gf100_grctx_generate_r4060a8(priv);
- gf100_grctx_generate_r418bb8(priv);
- gf100_grctx_generate_r406800(priv);
-
- gf100_gr_icmd(priv, oclass->icmd);
- nv_wr32(priv, 0x404154, 0x00000400);
- gf100_gr_mthd(priv, oclass->mthd);
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
+ oclass->unkn(gr);
+
+ gf100_grctx_generate_tpcid(gr);
+ gf100_grctx_generate_r406028(gr);
+ gf100_grctx_generate_r4060a8(gr);
+ gf100_grctx_generate_r418bb8(gr);
+ gf100_grctx_generate_r406800(gr);
+
+ gf100_gr_icmd(gr, oclass->icmd);
+ nv_wr32(gr, 0x404154, 0x00000400);
+ gf100_gr_mthd(gr, oclass->mthd);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
}
int
-gf100_grctx_generate(struct gf100_gr_priv *priv)
+gf100_grctx_generate(struct gf100_gr *gr)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
- struct nvkm_bar *bar = nvkm_bar(priv);
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
+ struct nvkm_bar *bar = nvkm_bar(gr);
struct nvkm_gpuobj *chan;
struct gf100_grctx info;
int ret, i;
/* allocate memory to for a "channel", which we'll use to generate
* the default context values
*/
- ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size,
+ ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x80000 + gr->size,
0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan);
if (ret) {
- nv_error(priv, "failed to allocate channel memory, %d\n", ret);
+ nv_error(gr, "failed to allocate channel memory, %d\n", ret);
return ret;
}
bar->flush(bar);
- nv_wr32(priv, 0x100cb8, (chan->addr + 0x1000) >> 8);
- nv_wr32(priv, 0x100cbc, 0x80000001);
- nv_wait(priv, 0x100c80, 0x00008000, 0x00008000);
+ nv_wr32(gr, 0x100cb8, (chan->addr + 0x1000) >> 8);
+ nv_wr32(gr, 0x100cbc, 0x80000001);
+ nv_wait(gr, 0x100c80, 0x00008000, 0x00008000);
/* setup default state for mmio list construction */
- info.priv = priv;
- info.data = priv->mmio_data;
- info.mmio = priv->mmio_list;
+ info.gr = gr;
+ info.data = gr->mmio_data;
+ info.mmio = gr->mmio_list;
info.addr = 0x2000 + (i * 8);
info.buffer_nr = 0;
/* make channel current */
- if (priv->firmware) {
- nv_wr32(priv, 0x409840, 0x00000030);
- nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12);
- nv_wr32(priv, 0x409504, 0x00000003);
- if (!nv_wait(priv, 0x409800, 0x00000010, 0x00000010))
- nv_error(priv, "load_ctx timeout\n");
+ if (gr->firmware) {
+ nv_wr32(gr, 0x409840, 0x00000030);
+ nv_wr32(gr, 0x409500, 0x80000000 | chan->addr >> 12);
+ nv_wr32(gr, 0x409504, 0x00000003);
+ if (!nv_wait(gr, 0x409800, 0x00000010, 0x00000010))
+ nv_error(gr, "load_ctx timeout\n");
nv_wo32(chan, 0x8001c, 1);
nv_wo32(chan, 0x80020, 0);
nv_wo32(chan, 0x8002c, 0);
bar->flush(bar);
} else {
- nv_wr32(priv, 0x409840, 0x80000000);
- nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12);
- nv_wr32(priv, 0x409504, 0x00000001);
- if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000))
- nv_error(priv, "HUB_SET_CHAN timeout\n");
+ nv_wr32(gr, 0x409840, 0x80000000);
+ nv_wr32(gr, 0x409500, 0x80000000 | chan->addr >> 12);
+ nv_wr32(gr, 0x409504, 0x00000001);
+ if (!nv_wait(gr, 0x409800, 0x80000000, 0x80000000))
+ nv_error(gr, "HUB_SET_CHAN timeout\n");
}
- oclass->main(priv, &info);
+ oclass->main(gr, &info);
/* trigger a context unload by unsetting the "next channel valid" bit
* and faking a context switch interrupt
*/
- nv_mask(priv, 0x409b04, 0x80000000, 0x00000000);
- nv_wr32(priv, 0x409000, 0x00000100);
- if (!nv_wait(priv, 0x409b00, 0x80000000, 0x00000000)) {
- nv_error(priv, "grctx template channel unload timeout\n");
+ nv_mask(gr, 0x409b04, 0x80000000, 0x00000000);
+ nv_wr32(gr, 0x409000, 0x00000100);
+ if (!nv_wait(gr, 0x409b00, 0x80000000, 0x00000000)) {
+ nv_error(gr, "grctx template channel unload timeout\n");
ret = -EBUSY;
goto done;
}
- priv->data = kmalloc(priv->size, GFP_KERNEL);
- if (priv->data) {
- for (i = 0; i < priv->size; i += 4)
- priv->data[i / 4] = nv_ro32(chan, 0x80000 + i);
+ gr->data = kmalloc(gr->size, GFP_KERNEL);
+ if (gr->data) {
+ for (i = 0; i < gr->size; i += 4)
+ gr->data[i / 4] = nv_ro32(chan, 0x80000 + i);
ret = 0;
} else {
ret = -ENOMEM;
#include "gf100.h"
struct gf100_grctx {
- struct gf100_gr_priv *priv;
+ struct gf100_gr *gr;
struct gf100_gr_data *data;
struct gf100_gr_mmio *mmio;
int buffer_nr;
struct gf100_grctx_oclass {
struct nvkm_oclass base;
/* main context generation function */
- void (*main)(struct gf100_gr_priv *, struct gf100_grctx *);
+ void (*main)(struct gf100_gr *, struct gf100_grctx *);
/* context-specific modify-on-first-load list generation function */
- void (*unkn)(struct gf100_gr_priv *);
+ void (*unkn)(struct gf100_gr *);
/* mmio context data */
const struct gf100_gr_pack *hub;
const struct gf100_gr_pack *gpc;
};
static inline const struct gf100_grctx_oclass *
-gf100_grctx_impl(struct gf100_gr_priv *priv)
+gf100_grctx_impl(struct gf100_gr *gr)
{
- return (void *)nv_engine(priv)->cclass;
+ return (void *)nv_engine(gr)->cclass;
}
extern struct nvkm_oclass *gf100_grctx_oclass;
-int gf100_grctx_generate(struct gf100_gr_priv *);
-void gf100_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *);
+int gf100_grctx_generate(struct gf100_gr *);
+void gf100_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *);
void gf100_grctx_generate_bundle(struct gf100_grctx *);
void gf100_grctx_generate_pagepool(struct gf100_grctx *);
void gf100_grctx_generate_attrib(struct gf100_grctx *);
-void gf100_grctx_generate_unkn(struct gf100_gr_priv *);
-void gf100_grctx_generate_tpcid(struct gf100_gr_priv *);
-void gf100_grctx_generate_r406028(struct gf100_gr_priv *);
-void gf100_grctx_generate_r4060a8(struct gf100_gr_priv *);
-void gf100_grctx_generate_r418bb8(struct gf100_gr_priv *);
-void gf100_grctx_generate_r406800(struct gf100_gr_priv *);
+void gf100_grctx_generate_unkn(struct gf100_gr *);
+void gf100_grctx_generate_tpcid(struct gf100_gr *);
+void gf100_grctx_generate_r406028(struct gf100_gr *);
+void gf100_grctx_generate_r4060a8(struct gf100_gr *);
+void gf100_grctx_generate_r418bb8(struct gf100_gr *);
+void gf100_grctx_generate_r406800(struct gf100_gr *);
extern struct nvkm_oclass *gf108_grctx_oclass;
void gf108_grctx_generate_attrib(struct gf100_grctx *);
-void gf108_grctx_generate_unkn(struct gf100_gr_priv *);
+void gf108_grctx_generate_unkn(struct gf100_gr *);
extern struct nvkm_oclass *gf104_grctx_oclass;
extern struct nvkm_oclass *gf110_grctx_oclass;
extern struct nvkm_oclass *gk104_grctx_oclass;
extern struct nvkm_oclass *gk20a_grctx_oclass;
-void gk104_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *);
+void gk104_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *);
void gk104_grctx_generate_bundle(struct gf100_grctx *);
void gk104_grctx_generate_pagepool(struct gf100_grctx *);
-void gk104_grctx_generate_unkn(struct gf100_gr_priv *);
-void gk104_grctx_generate_r418bb8(struct gf100_gr_priv *);
-void gk104_grctx_generate_rop_active_fbps(struct gf100_gr_priv *);
+void gk104_grctx_generate_unkn(struct gf100_gr *);
+void gk104_grctx_generate_r418bb8(struct gf100_gr *);
+void gk104_grctx_generate_rop_active_fbps(struct gf100_gr *);
void gm107_grctx_generate_bundle(struct gf100_grctx *);
void gm107_grctx_generate_attrib(struct gf100_grctx *);
extern struct nvkm_oclass *gm204_grctx_oclass;
-void gm204_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *);
-void gm204_grctx_generate_tpcid(struct gf100_gr_priv *);
-void gm204_grctx_generate_405b60(struct gf100_gr_priv *);
+void gm204_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *);
+void gm204_grctx_generate_tpcid(struct gf100_gr *);
+void gm204_grctx_generate_405b60(struct gf100_gr *);
extern struct nvkm_oclass *gm206_grctx_oclass;
extern struct nvkm_oclass *gm20b_grctx_oclass;
void
gf108_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct gf100_gr_priv *priv = info->priv;
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv);
+ struct gf100_gr *gr = info->gr;
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(gr);
const u32 alpha = impl->alpha_nr;
const u32 beta = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
const u32 access = NV_MEM_ACCESS_RW;
const int s = 12;
- const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access);
+ const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access);
const int timeslice_mode = 1;
const int max_batches = 0xffff;
u32 bo = 0;
- u32 ao = bo + impl->attrib_nr_max * priv->tpc_total;
+ u32 ao = bo + impl->attrib_nr_max * gr->tpc_total;
int gpc, tpc;
mmio_refn(info, 0x418810, 0x80000000, s, b);
mmio_wr32(info, 0x405830, (beta << 16) | alpha);
mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
const u32 a = alpha;
const u32 b = beta;
const u32 t = timeslice_mode;
}
void
-gf108_grctx_generate_unkn(struct gf100_gr_priv *priv)
+gf108_grctx_generate_unkn(struct gf100_gr *gr)
{
- nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
- nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
- nv_mask(priv, 0x419814, 0x00000004, 0x00000004);
- nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000);
- nv_mask(priv, 0x405800, 0x08000000, 0x08000000);
- nv_mask(priv, 0x419c00, 0x00000008, 0x00000008);
+ nv_mask(gr, 0x418c6c, 0x00000001, 0x00000001);
+ nv_mask(gr, 0x41980c, 0x00000010, 0x00000010);
+ nv_mask(gr, 0x419814, 0x00000004, 0x00000004);
+ nv_mask(gr, 0x4064c0, 0x80000000, 0x80000000);
+ nv_mask(gr, 0x405800, 0x08000000, 0x08000000);
+ nv_mask(gr, 0x419c00, 0x00000008, 0x00000008);
}
struct nvkm_oclass *
void
gf117_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct gf100_gr_priv *priv = info->priv;
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv);
+ struct gf100_gr *gr = info->gr;
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(gr);
const u32 alpha = impl->alpha_nr;
const u32 beta = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
const u32 access = NV_MEM_ACCESS_RW;
const int s = 12;
- const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access);
+ const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access);
const int timeslice_mode = 1;
const int max_batches = 0xffff;
u32 bo = 0;
- u32 ao = bo + impl->attrib_nr_max * priv->tpc_total;
+ u32 ao = bo + impl->attrib_nr_max * gr->tpc_total;
int gpc, ppc;
mmio_refn(info, 0x418810, 0x80000000, s, b);
mmio_wr32(info, 0x405830, (beta << 16) | alpha);
mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++) {
- const u32 a = alpha * priv->ppc_tpc_nr[gpc][ppc];
- const u32 b = beta * priv->ppc_tpc_nr[gpc][ppc];
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) {
+ const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc];
+ const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc];
const u32 t = timeslice_mode;
const u32 o = PPC_UNIT(gpc, ppc, 0);
mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo);
mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo);
- bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc];
+ bo += impl->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc];
mmio_wr32(info, o + 0xe4, (a << 16) | ao);
- ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc];
+ ao += impl->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
}
}
}
void
-gf117_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
int i;
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
- gf100_gr_mmio(priv, oclass->hub);
- gf100_gr_mmio(priv, oclass->gpc);
- gf100_gr_mmio(priv, oclass->zcull);
- gf100_gr_mmio(priv, oclass->tpc);
- gf100_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(gr, oclass->hub);
+ gf100_gr_mmio(gr, oclass->gpc);
+ gf100_gr_mmio(gr, oclass->zcull);
+ gf100_gr_mmio(gr, oclass->tpc);
+ gf100_gr_mmio(gr, oclass->ppc);
- nv_wr32(priv, 0x404154, 0x00000000);
+ nv_wr32(gr, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
oclass->attrib(info);
- oclass->unkn(priv);
+ oclass->unkn(gr);
- gf100_grctx_generate_tpcid(priv);
- gf100_grctx_generate_r406028(priv);
- gf100_grctx_generate_r4060a8(priv);
- gk104_grctx_generate_r418bb8(priv);
- gf100_grctx_generate_r406800(priv);
+ gf100_grctx_generate_tpcid(gr);
+ gf100_grctx_generate_r406028(gr);
+ gf100_grctx_generate_r4060a8(gr);
+ gk104_grctx_generate_r418bb8(gr);
+ gf100_grctx_generate_r406800(gr);
for (i = 0; i < 8; i++)
- nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
+ nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
- gf100_gr_icmd(priv, oclass->icmd);
- nv_wr32(priv, 0x404154, 0x00000400);
- gf100_gr_mthd(priv, oclass->mthd);
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
+ gf100_gr_icmd(gr, oclass->icmd);
+ nv_wr32(gr, 0x404154, 0x00000400);
+ gf100_gr_mthd(gr, oclass->mthd);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
}
struct nvkm_oclass *
void
gk104_grctx_generate_bundle(struct gf100_grctx *info)
{
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr);
const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth,
impl->bundle_size / 0x20);
const u32 token_limit = impl->bundle_token_limit;
void
gk104_grctx_generate_pagepool(struct gf100_grctx *info)
{
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
}
void
-gk104_grctx_generate_unkn(struct gf100_gr_priv *priv)
+gk104_grctx_generate_unkn(struct gf100_gr *gr)
{
- nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
- nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
- nv_mask(priv, 0x41be08, 0x00000004, 0x00000004);
- nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000);
- nv_mask(priv, 0x405800, 0x08000000, 0x08000000);
- nv_mask(priv, 0x419c00, 0x00000008, 0x00000008);
+ nv_mask(gr, 0x418c6c, 0x00000001, 0x00000001);
+ nv_mask(gr, 0x41980c, 0x00000010, 0x00000010);
+ nv_mask(gr, 0x41be08, 0x00000004, 0x00000004);
+ nv_mask(gr, 0x4064c0, 0x80000000, 0x80000000);
+ nv_mask(gr, 0x405800, 0x08000000, 0x08000000);
+ nv_mask(gr, 0x419c00, 0x00000008, 0x00000008);
}
void
-gk104_grctx_generate_r418bb8(struct gf100_gr_priv *priv)
+gk104_grctx_generate_r418bb8(struct gf100_gr *gr)
{
u32 data[6] = {}, data2[2] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, i;
/* calculate first set of magics */
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
gpc = -1;
- for (tpc = 0; tpc < priv->tpc_total; tpc++) {
+ for (tpc = 0; tpc < gr->tpc_total; tpc++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
tpcnr[gpc]--;
/* and the second... */
shift = 0;
- ntpcv = priv->tpc_total;
+ ntpcv = gr->tpc_total;
while (!(ntpcv & (1 << 4))) {
ntpcv <<= 1;
shift++;
data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
/* GPC_BROADCAST */
- nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) |
- priv->magic_not_rop_nr);
+ nv_wr32(gr, 0x418bb8, (gr->tpc_total << 8) |
+ gr->magic_not_rop_nr);
for (i = 0; i < 6; i++)
- nv_wr32(priv, 0x418b08 + (i * 4), data[i]);
+ nv_wr32(gr, 0x418b08 + (i * 4), data[i]);
/* GPC_BROADCAST.TP_BROADCAST */
- nv_wr32(priv, 0x41bfd0, (priv->tpc_total << 8) |
- priv->magic_not_rop_nr | data2[0]);
- nv_wr32(priv, 0x41bfe4, data2[1]);
+ nv_wr32(gr, 0x41bfd0, (gr->tpc_total << 8) |
+ gr->magic_not_rop_nr | data2[0]);
+ nv_wr32(gr, 0x41bfe4, data2[1]);
for (i = 0; i < 6; i++)
- nv_wr32(priv, 0x41bf00 + (i * 4), data[i]);
+ nv_wr32(gr, 0x41bf00 + (i * 4), data[i]);
/* UNK78xx */
- nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) |
- priv->magic_not_rop_nr);
+ nv_wr32(gr, 0x4078bc, (gr->tpc_total << 8) |
+ gr->magic_not_rop_nr);
for (i = 0; i < 6; i++)
- nv_wr32(priv, 0x40780c + (i * 4), data[i]);
+ nv_wr32(gr, 0x40780c + (i * 4), data[i]);
}
void
-gk104_grctx_generate_rop_active_fbps(struct gf100_gr_priv *priv)
+gk104_grctx_generate_rop_active_fbps(struct gf100_gr *gr)
{
- const u32 fbp_count = nv_rd32(priv, 0x120074);
- nv_mask(priv, 0x408850, 0x0000000f, fbp_count); /* zrop */
- nv_mask(priv, 0x408958, 0x0000000f, fbp_count); /* crop */
+ const u32 fbp_count = nv_rd32(gr, 0x120074);
+ nv_mask(gr, 0x408850, 0x0000000f, fbp_count); /* zrop */
+ nv_mask(gr, 0x408958, 0x0000000f, fbp_count); /* crop */
}
void
-gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
int i;
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
- gf100_gr_mmio(priv, oclass->hub);
- gf100_gr_mmio(priv, oclass->gpc);
- gf100_gr_mmio(priv, oclass->zcull);
- gf100_gr_mmio(priv, oclass->tpc);
- gf100_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(gr, oclass->hub);
+ gf100_gr_mmio(gr, oclass->gpc);
+ gf100_gr_mmio(gr, oclass->zcull);
+ gf100_gr_mmio(gr, oclass->tpc);
+ gf100_gr_mmio(gr, oclass->ppc);
- nv_wr32(priv, 0x404154, 0x00000000);
+ nv_wr32(gr, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
oclass->attrib(info);
- oclass->unkn(priv);
+ oclass->unkn(gr);
- gf100_grctx_generate_tpcid(priv);
- gf100_grctx_generate_r406028(priv);
- gk104_grctx_generate_r418bb8(priv);
- gf100_grctx_generate_r406800(priv);
+ gf100_grctx_generate_tpcid(gr);
+ gf100_grctx_generate_r406028(gr);
+ gk104_grctx_generate_r418bb8(gr);
+ gf100_grctx_generate_r406800(gr);
for (i = 0; i < 8; i++)
- nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
+ nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
- nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
- gk104_grctx_generate_rop_active_fbps(priv);
- nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
+ nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
+ gk104_grctx_generate_rop_active_fbps(gr);
+ nv_mask(gr, 0x419f78, 0x00000001, 0x00000000);
- gf100_gr_icmd(priv, oclass->icmd);
- nv_wr32(priv, 0x404154, 0x00000400);
- gf100_gr_mthd(priv, oclass->mthd);
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
+ gf100_gr_icmd(gr, oclass->icmd);
+ nv_wr32(gr, 0x404154, 0x00000400);
+ gf100_gr_mthd(gr, oclass->mthd);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
- nv_mask(priv, 0x418800, 0x00200000, 0x00200000);
- nv_mask(priv, 0x41be10, 0x00800000, 0x00800000);
+ nv_mask(gr, 0x418800, 0x00200000, 0x00200000);
+ nv_mask(gr, 0x41be10, 0x00800000, 0x00800000);
}
struct nvkm_oclass *
#include <subdev/mc.h>
static void
-gk20a_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
int idle_timeout_save;
int i;
- gf100_gr_mmio(priv, priv->fuc_sw_ctx);
+ gf100_gr_mmio(gr, gr->fuc_sw_ctx);
- gf100_gr_wait_idle(priv);
+ gf100_gr_wait_idle(gr);
- idle_timeout_save = nv_rd32(priv, 0x404154);
- nv_wr32(priv, 0x404154, 0x00000000);
+ idle_timeout_save = nv_rd32(gr, 0x404154);
+ nv_wr32(gr, 0x404154, 0x00000000);
oclass->attrib(info);
- oclass->unkn(priv);
+ oclass->unkn(gr);
- gf100_grctx_generate_tpcid(priv);
- gf100_grctx_generate_r406028(priv);
- gk104_grctx_generate_r418bb8(priv);
- gf100_grctx_generate_r406800(priv);
+ gf100_grctx_generate_tpcid(gr);
+ gf100_grctx_generate_r406028(gr);
+ gk104_grctx_generate_r418bb8(gr);
+ gf100_grctx_generate_r406800(gr);
for (i = 0; i < 8; i++)
- nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
+ nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
- nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
+ nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
- gk104_grctx_generate_rop_active_fbps(priv);
+ gk104_grctx_generate_rop_active_fbps(gr);
- nv_mask(priv, 0x5044b0, 0x8000000, 0x8000000);
+ nv_mask(gr, 0x5044b0, 0x8000000, 0x8000000);
- gf100_gr_wait_idle(priv);
+ gf100_gr_wait_idle(gr);
- nv_wr32(priv, 0x404154, idle_timeout_save);
- gf100_gr_wait_idle(priv);
+ nv_wr32(gr, 0x404154, idle_timeout_save);
+ gf100_gr_wait_idle(gr);
- gf100_gr_mthd(priv, priv->fuc_method);
- gf100_gr_wait_idle(priv);
+ gf100_gr_mthd(gr, gr->fuc_method);
+ gf100_gr_wait_idle(gr);
- gf100_gr_icmd(priv, priv->fuc_bundle);
+ gf100_gr_icmd(gr, gr->fuc_bundle);
oclass->pagepool(info);
oclass->bundle(info);
}
void
gm107_grctx_generate_bundle(struct gf100_grctx *info)
{
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr);
const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth,
impl->bundle_size / 0x20);
const u32 token_limit = impl->bundle_token_limit;
void
gm107_grctx_generate_pagepool(struct gf100_grctx *info)
{
- const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
void
gm107_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct gf100_gr_priv *priv = info->priv;
- const struct gf100_grctx_oclass *impl = (void *)gf100_grctx_impl(priv);
+ struct gf100_gr *gr = info->gr;
+ const struct gf100_grctx_oclass *impl = (void *)gf100_grctx_impl(gr);
const u32 alpha = impl->alpha_nr;
const u32 attrib = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
const u32 access = NV_MEM_ACCESS_RW;
const int s = 12;
- const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access);
+ const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access);
const int max_batches = 0xffff;
u32 bo = 0;
- u32 ao = bo + impl->attrib_nr_max * priv->tpc_total;
+ u32 ao = bo + impl->attrib_nr_max * gr->tpc_total;
int gpc, ppc, n = 0;
mmio_refn(info, 0x418810, 0x80000000, s, b);
mmio_wr32(info, 0x405830, (attrib << 16) | alpha);
mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++, n++) {
- const u32 as = alpha * priv->ppc_tpc_nr[gpc][ppc];
- const u32 bs = attrib * priv->ppc_tpc_nr[gpc][ppc];
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
+ const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
+ const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc];
const u32 u = 0x418ea0 + (n * 0x04);
const u32 o = PPC_UNIT(gpc, ppc, 0);
mmio_wr32(info, o + 0xc0, bs);
mmio_wr32(info, o + 0xf4, bo);
- bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc];
+ bo += impl->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc];
mmio_wr32(info, o + 0xe4, as);
mmio_wr32(info, o + 0xf8, ao);
- ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc];
+ ao += impl->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
mmio_wr32(info, u, ((bs / 3 /*XXX*/) << 16) | bs);
}
}
}
void
-gm107_grctx_generate_tpcid(struct gf100_gr_priv *priv)
+gm107_grctx_generate_tpcid(struct gf100_gr *gr)
{
int gpc, tpc, id;
for (tpc = 0, id = 0; tpc < 4; tpc++) {
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- if (tpc < priv->tpc_nr[gpc]) {
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id);
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ if (tpc < gr->tpc_nr[gpc]) {
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x698), id);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x088), id);
id++;
}
- nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]);
}
}
}
static void
-gm107_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
int i;
- gf100_gr_mmio(priv, oclass->hub);
- gf100_gr_mmio(priv, oclass->gpc);
- gf100_gr_mmio(priv, oclass->zcull);
- gf100_gr_mmio(priv, oclass->tpc);
- gf100_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(gr, oclass->hub);
+ gf100_gr_mmio(gr, oclass->gpc);
+ gf100_gr_mmio(gr, oclass->zcull);
+ gf100_gr_mmio(gr, oclass->tpc);
+ gf100_gr_mmio(gr, oclass->ppc);
- nv_wr32(priv, 0x404154, 0x00000000);
+ nv_wr32(gr, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
oclass->attrib(info);
- oclass->unkn(priv);
+ oclass->unkn(gr);
- gm107_grctx_generate_tpcid(priv);
- gf100_grctx_generate_r406028(priv);
- gk104_grctx_generate_r418bb8(priv);
- gf100_grctx_generate_r406800(priv);
+ gm107_grctx_generate_tpcid(gr);
+ gf100_grctx_generate_r406028(gr);
+ gk104_grctx_generate_r418bb8(gr);
+ gf100_grctx_generate_r406800(gr);
- nv_wr32(priv, 0x4064d0, 0x00000001);
+ nv_wr32(gr, 0x4064d0, 0x00000001);
for (i = 1; i < 8; i++)
- nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
- nv_wr32(priv, 0x406500, 0x00000001);
+ nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
+ nv_wr32(gr, 0x406500, 0x00000001);
- nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
+ nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
- gk104_grctx_generate_rop_active_fbps(priv);
+ gk104_grctx_generate_rop_active_fbps(gr);
- gf100_gr_icmd(priv, oclass->icmd);
- nv_wr32(priv, 0x404154, 0x00000400);
- gf100_gr_mthd(priv, oclass->mthd);
+ gf100_gr_icmd(gr, oclass->icmd);
+ nv_wr32(gr, 0x404154, 0x00000400);
+ gf100_gr_mthd(gr, oclass->mthd);
- nv_mask(priv, 0x419e00, 0x00808080, 0x00808080);
- nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000);
- nv_mask(priv, 0x419f80, 0x80000000, 0x80000000);
- nv_mask(priv, 0x419f88, 0x80000000, 0x80000000);
+ nv_mask(gr, 0x419e00, 0x00808080, 0x00808080);
+ nv_mask(gr, 0x419ccc, 0x80000000, 0x80000000);
+ nv_mask(gr, 0x419f80, 0x80000000, 0x80000000);
+ nv_mask(gr, 0x419f88, 0x80000000, 0x80000000);
}
struct nvkm_oclass *
******************************************************************************/
void
-gm204_grctx_generate_tpcid(struct gf100_gr_priv *priv)
+gm204_grctx_generate_tpcid(struct gf100_gr *gr)
{
int gpc, tpc, id;
for (tpc = 0, id = 0; tpc < 4; tpc++) {
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- if (tpc < priv->tpc_nr[gpc]) {
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id);
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ if (tpc < gr->tpc_nr[gpc]) {
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x698), id);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x088), id);
id++;
}
}
}
static void
-gm204_grctx_generate_rop_active_fbps(struct gf100_gr_priv *priv)
+gm204_grctx_generate_rop_active_fbps(struct gf100_gr *gr)
{
- const u32 fbp_count = nv_rd32(priv, 0x12006c);
- nv_mask(priv, 0x408850, 0x0000000f, fbp_count); /* zrop */
- nv_mask(priv, 0x408958, 0x0000000f, fbp_count); /* crop */
+ const u32 fbp_count = nv_rd32(gr, 0x12006c);
+ nv_mask(gr, 0x408850, 0x0000000f, fbp_count); /* zrop */
+ nv_mask(gr, 0x408958, 0x0000000f, fbp_count); /* crop */
}
void
-gm204_grctx_generate_405b60(struct gf100_gr_priv *priv)
+gm204_grctx_generate_405b60(struct gf100_gr *gr)
{
- const u32 dist_nr = DIV_ROUND_UP(priv->tpc_total, 4);
- u32 dist[TPC_MAX] = {};
+ const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4);
+ u32 dist[TPC_MAX / 4] = {};
u32 gpcs[GPC_MAX] = {};
u8 tpcnr[GPC_MAX];
int tpc, gpc, i;
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
/* won't result in the same distribution as the binary driver where
* some of the gpcs have more tpcs than others, but this shall do
* for the moment. the code for earlier gpus has this issue too.
*/
- for (gpc = -1, i = 0; i < priv->tpc_total; i++) {
+ for (gpc = -1, i = 0; i < gr->tpc_total; i++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while(!tpcnr[gpc]);
- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
+ tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
dist[i / 4] |= ((gpc << 4) | tpc) << ((i % 4) * 8);
gpcs[gpc] |= i << (tpc * 8);
}
for (i = 0; i < dist_nr; i++)
- nv_wr32(priv, 0x405b60 + (i * 4), dist[i]);
- for (i = 0; i < priv->gpc_nr; i++)
- nv_wr32(priv, 0x405ba0 + (i * 4), gpcs[i]);
+ nv_wr32(gr, 0x405b60 + (i * 4), dist[i]);
+ for (i = 0; i < gr->gpc_nr; i++)
+ nv_wr32(gr, 0x405ba0 + (i * 4), gpcs[i]);
}
void
-gm204_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+gm204_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
u32 tmp;
int i;
- gf100_gr_mmio(priv, oclass->hub);
- gf100_gr_mmio(priv, oclass->gpc);
- gf100_gr_mmio(priv, oclass->zcull);
- gf100_gr_mmio(priv, oclass->tpc);
- gf100_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(gr, oclass->hub);
+ gf100_gr_mmio(gr, oclass->gpc);
+ gf100_gr_mmio(gr, oclass->zcull);
+ gf100_gr_mmio(gr, oclass->tpc);
+ gf100_gr_mmio(gr, oclass->ppc);
- nv_wr32(priv, 0x404154, 0x00000000);
+ nv_wr32(gr, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
oclass->attrib(info);
- oclass->unkn(priv);
+ oclass->unkn(gr);
- gm204_grctx_generate_tpcid(priv);
- gf100_grctx_generate_r406028(priv);
- gk104_grctx_generate_r418bb8(priv);
+ gm204_grctx_generate_tpcid(gr);
+ gf100_grctx_generate_r406028(gr);
+ gk104_grctx_generate_r418bb8(gr);
for (i = 0; i < 8; i++)
- nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
- nv_wr32(priv, 0x406500, 0x00000000);
+ nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
+ nv_wr32(gr, 0x406500, 0x00000000);
- nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
+ nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
- gm204_grctx_generate_rop_active_fbps(priv);
+ gm204_grctx_generate_rop_active_fbps(gr);
- for (tmp = 0, i = 0; i < priv->gpc_nr; i++)
- tmp |= ((1 << priv->tpc_nr[i]) - 1) << (i * 4);
- nv_wr32(priv, 0x4041c4, tmp);
+ for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
+ tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
+ nv_wr32(gr, 0x4041c4, tmp);
- gm204_grctx_generate_405b60(priv);
+ gm204_grctx_generate_405b60(gr);
- gf100_gr_icmd(priv, oclass->icmd);
- nv_wr32(priv, 0x404154, 0x00000800);
- gf100_gr_mthd(priv, oclass->mthd);
+ gf100_gr_icmd(gr, oclass->icmd);
+ nv_wr32(gr, 0x404154, 0x00000800);
+ gf100_gr_mthd(gr, oclass->mthd);
- nv_mask(priv, 0x418e94, 0xffffffff, 0xc4230000);
- nv_mask(priv, 0x418e4c, 0xffffffff, 0x70000000);
+ nv_mask(gr, 0x418e94, 0xffffffff, 0xc4230000);
+ nv_mask(gr, 0x418e4c, 0xffffffff, 0x70000000);
}
struct nvkm_oclass *
#include "ctxgf100.h"
static void
-gm20b_grctx_generate_r406028(struct gf100_gr_priv *priv)
+gm20b_grctx_generate_r406028(struct gf100_gr *gr)
{
u32 tpc_per_gpc = 0;
int i;
- for (i = 0; i < priv->gpc_nr; i++)
- tpc_per_gpc |= priv->tpc_nr[i] << (4 * i);
+ for (i = 0; i < gr->gpc_nr; i++)
+ tpc_per_gpc |= gr->tpc_nr[i] << (4 * i);
- nv_wr32(priv, 0x406028, tpc_per_gpc);
- nv_wr32(priv, 0x405870, tpc_per_gpc);
+ nv_wr32(gr, 0x406028, tpc_per_gpc);
+ nv_wr32(gr, 0x405870, tpc_per_gpc);
}
static void
-gm20b_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
- struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
int idle_timeout_save;
int i, tmp;
- gf100_gr_mmio(priv, priv->fuc_sw_ctx);
+ gf100_gr_mmio(gr, gr->fuc_sw_ctx);
- gf100_gr_wait_idle(priv);
+ gf100_gr_wait_idle(gr);
- idle_timeout_save = nv_rd32(priv, 0x404154);
- nv_wr32(priv, 0x404154, 0x00000000);
+ idle_timeout_save = nv_rd32(gr, 0x404154);
+ nv_wr32(gr, 0x404154, 0x00000000);
oclass->attrib(info);
- oclass->unkn(priv);
+ oclass->unkn(gr);
- gm204_grctx_generate_tpcid(priv);
- gm20b_grctx_generate_r406028(priv);
- gk104_grctx_generate_r418bb8(priv);
+ gm204_grctx_generate_tpcid(gr);
+ gm20b_grctx_generate_r406028(gr);
+ gk104_grctx_generate_r418bb8(gr);
for (i = 0; i < 8; i++)
- nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
+ nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
- nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
+ nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
- gk104_grctx_generate_rop_active_fbps(priv);
- nv_wr32(priv, 0x408908, nv_rd32(priv, 0x410108) | 0x80000000);
+ gk104_grctx_generate_rop_active_fbps(gr);
+ nv_wr32(gr, 0x408908, nv_rd32(gr, 0x410108) | 0x80000000);
- for (tmp = 0, i = 0; i < priv->gpc_nr; i++)
- tmp |= ((1 << priv->tpc_nr[i]) - 1) << (i * 4);
- nv_wr32(priv, 0x4041c4, tmp);
+ for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
+ tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
+ nv_wr32(gr, 0x4041c4, tmp);
- gm204_grctx_generate_405b60(priv);
+ gm204_grctx_generate_405b60(gr);
- gf100_gr_wait_idle(priv);
+ gf100_gr_wait_idle(gr);
- nv_wr32(priv, 0x404154, idle_timeout_save);
- gf100_gr_wait_idle(priv);
+ nv_wr32(gr, 0x404154, idle_timeout_save);
+ gf100_gr_wait_idle(gr);
- gf100_gr_mthd(priv, priv->fuc_method);
- gf100_gr_wait_idle(priv);
+ gf100_gr_mthd(gr, gr->fuc_method);
+ gf100_gr_wait_idle(gr);
- gf100_gr_icmd(priv, priv->fuc_bundle);
+ gf100_gr_icmd(gr, gr->fuc_bundle);
oclass->pagepool(info);
oclass->bundle(info);
}
.attrib_nr = 0x400,
.alpha_nr_max = 0xc00,
.alpha_nr = 0x800,
-}.base;
\ No newline at end of file
+}.base;
******************************************************************************/
static void
-gf100_gr_zbc_clear_color(struct gf100_gr_priv *priv, int zbc)
+gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
{
- if (priv->zbc_color[zbc].format) {
- nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]);
- nv_wr32(priv, 0x405808, priv->zbc_color[zbc].ds[1]);
- nv_wr32(priv, 0x40580c, priv->zbc_color[zbc].ds[2]);
- nv_wr32(priv, 0x405810, priv->zbc_color[zbc].ds[3]);
- }
- nv_wr32(priv, 0x405814, priv->zbc_color[zbc].format);
- nv_wr32(priv, 0x405820, zbc);
- nv_wr32(priv, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */
+ if (gr->zbc_color[zbc].format) {
+ nv_wr32(gr, 0x405804, gr->zbc_color[zbc].ds[0]);
+ nv_wr32(gr, 0x405808, gr->zbc_color[zbc].ds[1]);
+ nv_wr32(gr, 0x40580c, gr->zbc_color[zbc].ds[2]);
+ nv_wr32(gr, 0x405810, gr->zbc_color[zbc].ds[3]);
+ }
+ nv_wr32(gr, 0x405814, gr->zbc_color[zbc].format);
+ nv_wr32(gr, 0x405820, zbc);
+ nv_wr32(gr, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */
}
static int
-gf100_gr_zbc_color_get(struct gf100_gr_priv *priv, int format,
+gf100_gr_zbc_color_get(struct gf100_gr *gr, int format,
const u32 ds[4], const u32 l2[4])
{
- struct nvkm_ltc *ltc = nvkm_ltc(priv);
+ struct nvkm_ltc *ltc = nvkm_ltc(gr);
int zbc = -ENOSPC, i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
- if (priv->zbc_color[i].format) {
- if (priv->zbc_color[i].format != format)
+ if (gr->zbc_color[i].format) {
+ if (gr->zbc_color[i].format != format)
continue;
- if (memcmp(priv->zbc_color[i].ds, ds, sizeof(
- priv->zbc_color[i].ds)))
+ if (memcmp(gr->zbc_color[i].ds, ds, sizeof(
+ gr->zbc_color[i].ds)))
continue;
- if (memcmp(priv->zbc_color[i].l2, l2, sizeof(
- priv->zbc_color[i].l2))) {
+ if (memcmp(gr->zbc_color[i].l2, l2, sizeof(
+ gr->zbc_color[i].l2))) {
WARN_ON(1);
return -EINVAL;
}
if (zbc < 0)
return zbc;
- memcpy(priv->zbc_color[zbc].ds, ds, sizeof(priv->zbc_color[zbc].ds));
- memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2));
- priv->zbc_color[zbc].format = format;
+ memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds));
+ memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2));
+ gr->zbc_color[zbc].format = format;
ltc->zbc_color_get(ltc, zbc, l2);
- gf100_gr_zbc_clear_color(priv, zbc);
+ gf100_gr_zbc_clear_color(gr, zbc);
return zbc;
}
static void
-gf100_gr_zbc_clear_depth(struct gf100_gr_priv *priv, int zbc)
+gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)
{
- if (priv->zbc_depth[zbc].format)
- nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds);
- nv_wr32(priv, 0x40581c, priv->zbc_depth[zbc].format);
- nv_wr32(priv, 0x405820, zbc);
- nv_wr32(priv, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */
+ if (gr->zbc_depth[zbc].format)
+ nv_wr32(gr, 0x405818, gr->zbc_depth[zbc].ds);
+ nv_wr32(gr, 0x40581c, gr->zbc_depth[zbc].format);
+ nv_wr32(gr, 0x405820, zbc);
+ nv_wr32(gr, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */
}
static int
-gf100_gr_zbc_depth_get(struct gf100_gr_priv *priv, int format,
+gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
const u32 ds, const u32 l2)
{
- struct nvkm_ltc *ltc = nvkm_ltc(priv);
+ struct nvkm_ltc *ltc = nvkm_ltc(gr);
int zbc = -ENOSPC, i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
- if (priv->zbc_depth[i].format) {
- if (priv->zbc_depth[i].format != format)
+ if (gr->zbc_depth[i].format) {
+ if (gr->zbc_depth[i].format != format)
continue;
- if (priv->zbc_depth[i].ds != ds)
+ if (gr->zbc_depth[i].ds != ds)
continue;
- if (priv->zbc_depth[i].l2 != l2) {
+ if (gr->zbc_depth[i].l2 != l2) {
WARN_ON(1);
return -EINVAL;
}
if (zbc < 0)
return zbc;
- priv->zbc_depth[zbc].format = format;
- priv->zbc_depth[zbc].ds = ds;
- priv->zbc_depth[zbc].l2 = l2;
+ gr->zbc_depth[zbc].format = format;
+ gr->zbc_depth[zbc].ds = ds;
+ gr->zbc_depth[zbc].l2 = l2;
ltc->zbc_depth_get(ltc, zbc, l2);
- gf100_gr_zbc_clear_depth(priv, zbc);
+ gf100_gr_zbc_clear_depth(gr, zbc);
return zbc;
}
static int
gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
{
- struct gf100_gr_priv *priv = (void *)object->engine;
+ struct gf100_gr *gr = (void *)object->engine;
union {
struct fermi_a_zbc_color_v0 v0;
} *args = data;
case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8:
case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10:
case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11:
- ret = gf100_gr_zbc_color_get(priv, args->v0.format,
+ ret = gf100_gr_zbc_color_get(gr, args->v0.format,
args->v0.ds,
args->v0.l2);
if (ret >= 0) {
static int
gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size)
{
- struct gf100_gr_priv *priv = (void *)object->engine;
+ struct gf100_gr *gr = (void *)object->engine;
union {
struct fermi_a_zbc_depth_v0 v0;
} *args = data;
if (nvif_unpack(args->v0, 0, 0, false)) {
switch (args->v0.format) {
case FERMI_A_ZBC_DEPTH_V0_FMT_FP32:
- ret = gf100_gr_zbc_depth_get(priv, args->v0.format,
+ ret = gf100_gr_zbc_depth_get(gr, args->v0.format,
args->v0.ds,
args->v0.l2);
return (ret >= 0) ? 0 : -ENOSPC;
gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd,
void *pdata, u32 size)
{
- struct gf100_gr_priv *priv = (void *)object->engine;
+ struct gf100_gr *gr = (void *)object->engine;
if (size >= sizeof(u32)) {
u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000;
- nv_wr32(priv, 0x419e44, data);
- nv_wr32(priv, 0x419e4c, data);
+ nv_wr32(gr, 0x419e44, data);
+ nv_wr32(gr, 0x419e4c, data);
return 0;
}
return -EINVAL;
struct nvkm_object **pobject)
{
struct nvkm_vm *vm = nvkm_client(parent)->vm;
- struct gf100_gr_priv *priv = (void *)engine;
- struct gf100_gr_data *data = priv->mmio_data;
- struct gf100_gr_mmio *mmio = priv->mmio_list;
+ struct gf100_gr *gr = (void *)engine;
+ struct gf100_gr_data *data = gr->mmio_data;
+ struct gf100_gr_mmio *mmio = gr->mmio_list;
struct gf100_gr_chan *chan;
int ret, i;
/* allocate memory for context, and fill with default values */
ret = nvkm_gr_context_create(parent, engine, oclass, NULL,
- priv->size, 0x100,
+ gr->size, 0x100,
NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
/* allocate buffers referenced by mmio list */
- for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) {
+ for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) {
ret = nvkm_gpuobj_new(nv_object(chan), NULL, data->size,
data->align, 0, &chan->data[i].mem);
if (ret)
}
/* finally, fill in the mmio list and point the context at it */
- for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) {
+ for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) {
u32 addr = mmio->addr;
u32 data = mmio->data;
mmio++;
}
- for (i = 0; i < priv->size; i += 4)
- nv_wo32(chan, i, priv->data[i / 4]);
+ for (i = 0; i < gr->size; i += 4)
+ nv_wo32(chan, i, gr->data[i / 4]);
- if (!priv->firmware) {
+ if (!gr->firmware) {
nv_wo32(chan, 0x00, chan->mmio_nr / 2);
nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8);
} else {
******************************************************************************/
void
-gf100_gr_zbc_init(struct gf100_gr_priv *priv)
+gf100_gr_zbc_init(struct gf100_gr *gr)
{
const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000 };
0x00000000, 0x00000000, 0x00000000, 0x00000000 };
const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
- struct nvkm_ltc *ltc = nvkm_ltc(priv);
+ struct nvkm_ltc *ltc = nvkm_ltc(gr);
int index;
- if (!priv->zbc_color[0].format) {
- gf100_gr_zbc_color_get(priv, 1, & zero[0], &zero[4]);
- gf100_gr_zbc_color_get(priv, 2, & one[0], &one[4]);
- gf100_gr_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]);
- gf100_gr_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]);
- gf100_gr_zbc_depth_get(priv, 1, 0x00000000, 0x00000000);
- gf100_gr_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000);
+ if (!gr->zbc_color[0].format) {
+ gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]);
+ gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]);
+ gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]);
+ gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]);
+ gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000);
+ gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000);
}
for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
- gf100_gr_zbc_clear_color(priv, index);
+ gf100_gr_zbc_clear_color(gr, index);
for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
- gf100_gr_zbc_clear_depth(priv, index);
+ gf100_gr_zbc_clear_depth(gr, index);
}
/**
* progress.
*/
int
-gf100_gr_wait_idle(struct gf100_gr_priv *priv)
+gf100_gr_wait_idle(struct gf100_gr *gr)
{
unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000);
bool gr_enabled, ctxsw_active, gr_busy;
* required to make sure FIFO_ENGINE_STATUS (0x2640) is
* up-to-date
*/
- nv_rd32(priv, 0x400700);
+ nv_rd32(gr, 0x400700);
- gr_enabled = nv_rd32(priv, 0x200) & 0x1000;
- ctxsw_active = nv_rd32(priv, 0x2640) & 0x8000;
- gr_busy = nv_rd32(priv, 0x40060c) & 0x1;
+ gr_enabled = nv_rd32(gr, 0x200) & 0x1000;
+ ctxsw_active = nv_rd32(gr, 0x2640) & 0x8000;
+ gr_busy = nv_rd32(gr, 0x40060c) & 0x1;
if (!gr_enabled || (!gr_busy && !ctxsw_active))
return 0;
} while (time_before(jiffies, end_jiffies));
- nv_error(priv, "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
+ nv_error(gr, "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
gr_enabled, ctxsw_active, gr_busy);
return -EAGAIN;
}
void
-gf100_gr_mmio(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
+gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p)
{
const struct gf100_gr_pack *pack;
const struct gf100_gr_init *init;
u32 next = init->addr + init->count * init->pitch;
u32 addr = init->addr;
while (addr < next) {
- nv_wr32(priv, addr, init->data);
+ nv_wr32(gr, addr, init->data);
addr += init->pitch;
}
}
}
void
-gf100_gr_icmd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
+gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
{
const struct gf100_gr_pack *pack;
const struct gf100_gr_init *init;
u32 data = 0;
- nv_wr32(priv, 0x400208, 0x80000000);
+ nv_wr32(gr, 0x400208, 0x80000000);
pack_for_each_init(init, pack, p) {
u32 next = init->addr + init->count * init->pitch;
u32 addr = init->addr;
if ((pack == p && init == p->init) || data != init->data) {
- nv_wr32(priv, 0x400204, init->data);
+ nv_wr32(gr, 0x400204, init->data);
data = init->data;
}
while (addr < next) {
- nv_wr32(priv, 0x400200, addr);
+ nv_wr32(gr, 0x400200, addr);
/**
* Wait for GR to go idle after submitting a
* GO_IDLE bundle
*/
if ((addr & 0xffff) == 0xe100)
- gf100_gr_wait_idle(priv);
- nv_wait(priv, 0x400700, 0x00000004, 0x00000000);
+ gf100_gr_wait_idle(gr);
+ nv_wait(gr, 0x400700, 0x00000004, 0x00000000);
addr += init->pitch;
}
}
- nv_wr32(priv, 0x400208, 0x00000000);
+ nv_wr32(gr, 0x400208, 0x00000000);
}
void
-gf100_gr_mthd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
+gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
{
const struct gf100_gr_pack *pack;
const struct gf100_gr_init *init;
u32 addr = init->addr;
if ((pack == p && init == p->init) || data != init->data) {
- nv_wr32(priv, 0x40448c, init->data);
+ nv_wr32(gr, 0x40448c, init->data);
data = init->data;
}
while (addr < next) {
- nv_wr32(priv, 0x404488, ctrl | (addr << 14));
+ nv_wr32(gr, 0x404488, ctrl | (addr << 14));
addr += init->pitch;
}
}
}
u64
-gf100_gr_units(struct nvkm_gr *gr)
+gf100_gr_units(struct nvkm_gr *obj)
{
- struct gf100_gr_priv *priv = (void *)gr;
+ struct gf100_gr *gr = container_of(obj, typeof(*gr), base);
u64 cfg;
- cfg = (u32)priv->gpc_nr;
- cfg |= (u32)priv->tpc_total << 8;
- cfg |= (u64)priv->rop_nr << 32;
+ cfg = (u32)gr->gpc_nr;
+ cfg |= (u32)gr->tpc_total << 8;
+ cfg |= (u64)gr->rop_nr << 32;
return cfg;
}
};
static void
-gf100_gr_trap_gpc_rop(struct gf100_gr_priv *priv, int gpc)
+gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc)
{
u32 trap[4];
int i;
- trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420));
- trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434));
- trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438));
- trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c));
+ trap[0] = nv_rd32(gr, GPC_UNIT(gpc, 0x0420));
+ trap[1] = nv_rd32(gr, GPC_UNIT(gpc, 0x0434));
+ trap[2] = nv_rd32(gr, GPC_UNIT(gpc, 0x0438));
+ trap[3] = nv_rd32(gr, GPC_UNIT(gpc, 0x043c));
- nv_error(priv, "GPC%d/PROP trap:", gpc);
+ nv_error(gr, "GPC%d/PROP trap:", gpc);
for (i = 0; i <= 29; ++i) {
if (!(trap[0] & (1 << i)))
continue;
}
pr_cont("\n");
- nv_error(priv, "x = %u, y = %u, format = %x, storage type = %x\n",
+ nv_error(gr, "x = %u, y = %u, format = %x, storage type = %x\n",
trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f,
trap[3] & 0xff);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000);
}
static const struct nvkm_enum gf100_mp_warp_error[] = {
};
static void
-gf100_gr_trap_mp(struct gf100_gr_priv *priv, int gpc, int tpc)
+gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
{
- u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648));
- u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650));
+ u32 werr = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x648));
+ u32 gerr = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x650));
- nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc);
+ nv_error(gr, "GPC%i/TPC%i/MP trap:", gpc, tpc);
nvkm_bitfield_print(gf100_mp_global_error, gerr);
if (werr) {
pr_cont(" ");
}
pr_cont("\n");
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x650), gerr);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x650), gerr);
}
static void
-gf100_gr_trap_tpc(struct gf100_gr_priv *priv, int gpc, int tpc)
+gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc)
{
- u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508));
+ u32 stat = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x0508));
if (stat & 0x00000001) {
- u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224));
- nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
+ u32 trap = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x0224));
+ nv_error(gr, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
stat &= ~0x00000001;
}
if (stat & 0x00000002) {
- gf100_gr_trap_mp(priv, gpc, tpc);
+ gf100_gr_trap_mp(gr, gpc, tpc);
stat &= ~0x00000002;
}
if (stat & 0x00000004) {
- u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084));
- nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
+ u32 trap = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x0084));
+ nv_error(gr, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
stat &= ~0x00000004;
}
if (stat & 0x00000008) {
- u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c));
- nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
+ u32 trap = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x048c));
+ nv_error(gr, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
stat &= ~0x00000008;
}
if (stat) {
- nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat);
+ nv_error(gr, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat);
}
}
static void
-gf100_gr_trap_gpc(struct gf100_gr_priv *priv, int gpc)
+gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc)
{
- u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90));
+ u32 stat = nv_rd32(gr, GPC_UNIT(gpc, 0x2c90));
int tpc;
if (stat & 0x00000001) {
- gf100_gr_trap_gpc_rop(priv, gpc);
+ gf100_gr_trap_gpc_rop(gr, gpc);
stat &= ~0x00000001;
}
if (stat & 0x00000002) {
- u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900));
- nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
+ u32 trap = nv_rd32(gr, GPC_UNIT(gpc, 0x0900));
+ nv_error(gr, "GPC%d/ZCULL: 0x%08x\n", gpc, trap);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000);
stat &= ~0x00000002;
}
if (stat & 0x00000004) {
- u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028));
- nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap);
- nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
+ u32 trap = nv_rd32(gr, GPC_UNIT(gpc, 0x1028));
+ nv_error(gr, "GPC%d/CCACHE: 0x%08x\n", gpc, trap);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000);
stat &= ~0x00000004;
}
if (stat & 0x00000008) {
- u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824));
- nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
+ u32 trap = nv_rd32(gr, GPC_UNIT(gpc, 0x0824));
+ nv_error(gr, "GPC%d/ESETUP: 0x%08x\n", gpc, trap);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000);
stat &= ~0x00000009;
}
- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
+ for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
u32 mask = 0x00010000 << tpc;
if (stat & mask) {
- gf100_gr_trap_tpc(priv, gpc, tpc);
- nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask);
+ gf100_gr_trap_tpc(gr, gpc, tpc);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), mask);
stat &= ~mask;
}
}
if (stat) {
- nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat);
+ nv_error(gr, "GPC%d/0x%08x: unknown\n", gpc, stat);
}
}
static void
-gf100_gr_trap_intr(struct gf100_gr_priv *priv)
+gf100_gr_trap_intr(struct gf100_gr *gr)
{
- u32 trap = nv_rd32(priv, 0x400108);
+ u32 trap = nv_rd32(gr, 0x400108);
int rop, gpc, i;
if (trap & 0x00000001) {
- u32 stat = nv_rd32(priv, 0x404000);
- nv_error(priv, "DISPATCH 0x%08x\n", stat);
- nv_wr32(priv, 0x404000, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x00000001);
+ u32 stat = nv_rd32(gr, 0x404000);
+ nv_error(gr, "DISPATCH 0x%08x\n", stat);
+ nv_wr32(gr, 0x404000, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x00000001);
trap &= ~0x00000001;
}
if (trap & 0x00000002) {
- u32 stat = nv_rd32(priv, 0x404600);
- nv_error(priv, "M2MF 0x%08x\n", stat);
- nv_wr32(priv, 0x404600, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x00000002);
+ u32 stat = nv_rd32(gr, 0x404600);
+ nv_error(gr, "M2MF 0x%08x\n", stat);
+ nv_wr32(gr, 0x404600, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x00000002);
trap &= ~0x00000002;
}
if (trap & 0x00000008) {
- u32 stat = nv_rd32(priv, 0x408030);
- nv_error(priv, "CCACHE 0x%08x\n", stat);
- nv_wr32(priv, 0x408030, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x00000008);
+ u32 stat = nv_rd32(gr, 0x408030);
+ nv_error(gr, "CCACHE 0x%08x\n", stat);
+ nv_wr32(gr, 0x408030, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x00000008);
trap &= ~0x00000008;
}
if (trap & 0x00000010) {
- u32 stat = nv_rd32(priv, 0x405840);
- nv_error(priv, "SHADER 0x%08x\n", stat);
- nv_wr32(priv, 0x405840, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x00000010);
+ u32 stat = nv_rd32(gr, 0x405840);
+ nv_error(gr, "SHADER 0x%08x\n", stat);
+ nv_wr32(gr, 0x405840, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x00000010);
trap &= ~0x00000010;
}
if (trap & 0x00000040) {
- u32 stat = nv_rd32(priv, 0x40601c);
- nv_error(priv, "UNK6 0x%08x\n", stat);
- nv_wr32(priv, 0x40601c, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x00000040);
+ u32 stat = nv_rd32(gr, 0x40601c);
+ nv_error(gr, "UNK6 0x%08x\n", stat);
+ nv_wr32(gr, 0x40601c, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x00000040);
trap &= ~0x00000040;
}
if (trap & 0x00000080) {
- u32 stat = nv_rd32(priv, 0x404490);
- nv_error(priv, "MACRO 0x%08x\n", stat);
- nv_wr32(priv, 0x404490, 0xc0000000);
- nv_wr32(priv, 0x400108, 0x00000080);
+ u32 stat = nv_rd32(gr, 0x404490);
+ nv_error(gr, "MACRO 0x%08x\n", stat);
+ nv_wr32(gr, 0x404490, 0xc0000000);
+ nv_wr32(gr, 0x400108, 0x00000080);
trap &= ~0x00000080;
}
if (trap & 0x00000100) {
- u32 stat = nv_rd32(priv, 0x407020);
+ u32 stat = nv_rd32(gr, 0x407020);
- nv_error(priv, "SKED:");
+ nv_error(gr, "SKED:");
for (i = 0; i <= 29; ++i) {
if (!(stat & (1 << i)))
continue;
pr_cont("\n");
if (stat & 0x3fffffff)
- nv_wr32(priv, 0x407020, 0x40000000);
- nv_wr32(priv, 0x400108, 0x00000100);
+ nv_wr32(gr, 0x407020, 0x40000000);
+ nv_wr32(gr, 0x400108, 0x00000100);
trap &= ~0x00000100;
}
if (trap & 0x01000000) {
- u32 stat = nv_rd32(priv, 0x400118);
- for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) {
+ u32 stat = nv_rd32(gr, 0x400118);
+ for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) {
u32 mask = 0x00000001 << gpc;
if (stat & mask) {
- gf100_gr_trap_gpc(priv, gpc);
- nv_wr32(priv, 0x400118, mask);
+ gf100_gr_trap_gpc(gr, gpc);
+ nv_wr32(gr, 0x400118, mask);
stat &= ~mask;
}
}
- nv_wr32(priv, 0x400108, 0x01000000);
+ nv_wr32(gr, 0x400108, 0x01000000);
trap &= ~0x01000000;
}
if (trap & 0x02000000) {
- for (rop = 0; rop < priv->rop_nr; rop++) {
- u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070));
- u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144));
- nv_error(priv, "ROP%d 0x%08x 0x%08x\n",
+ for (rop = 0; rop < gr->rop_nr; rop++) {
+ u32 statz = nv_rd32(gr, ROP_UNIT(rop, 0x070));
+ u32 statc = nv_rd32(gr, ROP_UNIT(rop, 0x144));
+ nv_error(gr, "ROP%d 0x%08x 0x%08x\n",
rop, statz, statc);
- nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
- nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x070), 0xc0000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x144), 0xc0000000);
}
- nv_wr32(priv, 0x400108, 0x02000000);
+ nv_wr32(gr, 0x400108, 0x02000000);
trap &= ~0x02000000;
}
if (trap) {
- nv_error(priv, "TRAP UNHANDLED 0x%08x\n", trap);
- nv_wr32(priv, 0x400108, trap);
+ nv_error(gr, "TRAP UNHANDLED 0x%08x\n", trap);
+ nv_wr32(gr, 0x400108, trap);
}
}
static void
-gf100_gr_ctxctl_debug_unit(struct gf100_gr_priv *priv, u32 base)
+gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base)
{
- nv_error(priv, "%06x - done 0x%08x\n", base,
- nv_rd32(priv, base + 0x400));
- nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
- nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804),
- nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c));
- nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
- nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814),
- nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c));
+ nv_error(gr, "%06x - done 0x%08x\n", base,
+ nv_rd32(gr, base + 0x400));
+ nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
+ nv_rd32(gr, base + 0x800), nv_rd32(gr, base + 0x804),
+ nv_rd32(gr, base + 0x808), nv_rd32(gr, base + 0x80c));
+ nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
+ nv_rd32(gr, base + 0x810), nv_rd32(gr, base + 0x814),
+ nv_rd32(gr, base + 0x818), nv_rd32(gr, base + 0x81c));
}
void
-gf100_gr_ctxctl_debug(struct gf100_gr_priv *priv)
+gf100_gr_ctxctl_debug(struct gf100_gr *gr)
{
- u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff;
+ u32 gpcnr = nv_rd32(gr, 0x409604) & 0xffff;
u32 gpc;
- gf100_gr_ctxctl_debug_unit(priv, 0x409000);
+ gf100_gr_ctxctl_debug_unit(gr, 0x409000);
for (gpc = 0; gpc < gpcnr; gpc++)
- gf100_gr_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
+ gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000));
}
static void
-gf100_gr_ctxctl_isr(struct gf100_gr_priv *priv)
+gf100_gr_ctxctl_isr(struct gf100_gr *gr)
{
- u32 stat = nv_rd32(priv, 0x409c18);
+ u32 stat = nv_rd32(gr, 0x409c18);
if (stat & 0x00000001) {
- u32 code = nv_rd32(priv, 0x409814);
+ u32 code = nv_rd32(gr, 0x409814);
if (code == E_BAD_FWMTHD) {
- u32 class = nv_rd32(priv, 0x409808);
- u32 addr = nv_rd32(priv, 0x40980c);
+ u32 class = nv_rd32(gr, 0x409808);
+ u32 addr = nv_rd32(gr, 0x40980c);
u32 subc = (addr & 0x00070000) >> 16;
u32 mthd = (addr & 0x00003ffc);
- u32 data = nv_rd32(priv, 0x409810);
+ u32 data = nv_rd32(gr, 0x409810);
- nv_error(priv, "FECS MTHD subc %d class 0x%04x "
+ nv_error(gr, "FECS MTHD subc %d class 0x%04x "
"mthd 0x%04x data 0x%08x\n",
subc, class, mthd, data);
- nv_wr32(priv, 0x409c20, 0x00000001);
+ nv_wr32(gr, 0x409c20, 0x00000001);
stat &= ~0x00000001;
} else {
- nv_error(priv, "FECS ucode error %d\n", code);
+ nv_error(gr, "FECS ucode error %d\n", code);
}
}
if (stat & 0x00080000) {
- nv_error(priv, "FECS watchdog timeout\n");
- gf100_gr_ctxctl_debug(priv);
- nv_wr32(priv, 0x409c20, 0x00080000);
+ nv_error(gr, "FECS watchdog timeout\n");
+ gf100_gr_ctxctl_debug(gr);
+ nv_wr32(gr, 0x409c20, 0x00080000);
stat &= ~0x00080000;
}
if (stat) {
- nv_error(priv, "FECS 0x%08x\n", stat);
- gf100_gr_ctxctl_debug(priv);
- nv_wr32(priv, 0x409c20, stat);
+ nv_error(gr, "FECS 0x%08x\n", stat);
+ gf100_gr_ctxctl_debug(gr);
+ nv_wr32(gr, 0x409c20, stat);
}
}
struct nvkm_engine *engine = nv_engine(subdev);
struct nvkm_object *engctx;
struct nvkm_handle *handle;
- struct gf100_gr_priv *priv = (void *)subdev;
- u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff;
- u32 stat = nv_rd32(priv, 0x400100);
- u32 addr = nv_rd32(priv, 0x400704);
+ struct gf100_gr *gr = (void *)subdev;
+ u64 inst = nv_rd32(gr, 0x409b00) & 0x0fffffff;
+ u32 stat = nv_rd32(gr, 0x400100);
+ u32 addr = nv_rd32(gr, 0x400704);
u32 mthd = (addr & 0x00003ffc);
u32 subc = (addr & 0x00070000) >> 16;
- u32 data = nv_rd32(priv, 0x400708);
- u32 code = nv_rd32(priv, 0x400110);
+ u32 data = nv_rd32(gr, 0x400708);
+ u32 code = nv_rd32(gr, 0x400110);
u32 class;
int chid;
- if (nv_device(priv)->card_type < NV_E0 || subc < 4)
- class = nv_rd32(priv, 0x404200 + (subc * 4));
+ if (nv_device(gr)->card_type < NV_E0 || subc < 4)
+ class = nv_rd32(gr, 0x404200 + (subc * 4));
else
class = 0x0000;
* notifier interrupt, only needed for cyclestats
* can be safely ignored
*/
- nv_wr32(priv, 0x400100, 0x00000001);
+ nv_wr32(gr, 0x400100, 0x00000001);
stat &= ~0x00000001;
}
if (stat & 0x00000010) {
handle = nvkm_handle_get_class(engctx, class);
if (!handle || nv_call(handle->object, mthd, data)) {
- nv_error(priv,
+ nv_error(gr,
"ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, inst << 12, nvkm_client_name(engctx),
subc, class, mthd, data);
}
nvkm_handle_put(handle);
- nv_wr32(priv, 0x400100, 0x00000010);
+ nv_wr32(gr, 0x400100, 0x00000010);
stat &= ~0x00000010;
}
if (stat & 0x00000020) {
- nv_error(priv,
+ nv_error(gr,
"ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, inst << 12, nvkm_client_name(engctx), subc,
class, mthd, data);
- nv_wr32(priv, 0x400100, 0x00000020);
+ nv_wr32(gr, 0x400100, 0x00000020);
stat &= ~0x00000020;
}
if (stat & 0x00100000) {
- nv_error(priv, "DATA_ERROR [");
+ nv_error(gr, "DATA_ERROR [");
nvkm_enum_print(nv50_data_error_names, code);
pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, inst << 12, nvkm_client_name(engctx), subc,
class, mthd, data);
- nv_wr32(priv, 0x400100, 0x00100000);
+ nv_wr32(gr, 0x400100, 0x00100000);
stat &= ~0x00100000;
}
if (stat & 0x00200000) {
- nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12,
+ nv_error(gr, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12,
nvkm_client_name(engctx));
- gf100_gr_trap_intr(priv);
- nv_wr32(priv, 0x400100, 0x00200000);
+ gf100_gr_trap_intr(gr);
+ nv_wr32(gr, 0x400100, 0x00200000);
stat &= ~0x00200000;
}
if (stat & 0x00080000) {
- gf100_gr_ctxctl_isr(priv);
- nv_wr32(priv, 0x400100, 0x00080000);
+ gf100_gr_ctxctl_isr(gr);
+ nv_wr32(gr, 0x400100, 0x00080000);
stat &= ~0x00080000;
}
if (stat) {
- nv_error(priv, "unknown stat 0x%08x\n", stat);
- nv_wr32(priv, 0x400100, stat);
+ nv_error(gr, "unknown stat 0x%08x\n", stat);
+ nv_wr32(gr, 0x400100, stat);
}
- nv_wr32(priv, 0x400500, 0x00010001);
+ nv_wr32(gr, 0x400500, 0x00010001);
nvkm_engctx_put(engctx);
}
void
-gf100_gr_init_fw(struct gf100_gr_priv *priv, u32 fuc_base,
+gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base,
struct gf100_gr_fuc *code, struct gf100_gr_fuc *data)
{
int i;
- nv_wr32(priv, fuc_base + 0x01c0, 0x01000000);
+ nv_wr32(gr, fuc_base + 0x01c0, 0x01000000);
for (i = 0; i < data->size / 4; i++)
- nv_wr32(priv, fuc_base + 0x01c4, data->data[i]);
+ nv_wr32(gr, fuc_base + 0x01c4, data->data[i]);
- nv_wr32(priv, fuc_base + 0x0180, 0x01000000);
+ nv_wr32(gr, fuc_base + 0x0180, 0x01000000);
for (i = 0; i < code->size / 4; i++) {
if ((i & 0x3f) == 0)
- nv_wr32(priv, fuc_base + 0x0188, i >> 6);
- nv_wr32(priv, fuc_base + 0x0184, code->data[i]);
+ nv_wr32(gr, fuc_base + 0x0188, i >> 6);
+ nv_wr32(gr, fuc_base + 0x0184, code->data[i]);
}
/* code must be padded to 0x40 words */
for (; i & 0x3f; i++)
- nv_wr32(priv, fuc_base + 0x0184, 0);
+ nv_wr32(gr, fuc_base + 0x0184, 0);
}
static void
-gf100_gr_init_csdata(struct gf100_gr_priv *priv,
+gf100_gr_init_csdata(struct gf100_gr *gr,
const struct gf100_gr_pack *pack,
u32 falcon, u32 starstar, u32 base)
{
u32 addr = ~0, prev = ~0, xfer = 0;
u32 star, temp;
- nv_wr32(priv, falcon + 0x01c0, 0x02000000 + starstar);
- star = nv_rd32(priv, falcon + 0x01c4);
- temp = nv_rd32(priv, falcon + 0x01c4);
+ nv_wr32(gr, falcon + 0x01c0, 0x02000000 + starstar);
+ star = nv_rd32(gr, falcon + 0x01c4);
+ temp = nv_rd32(gr, falcon + 0x01c4);
if (temp > star)
star = temp;
- nv_wr32(priv, falcon + 0x01c0, 0x01000000 + star);
+ nv_wr32(gr, falcon + 0x01c0, 0x01000000 + star);
pack_for_each_init(init, iter, pack) {
u32 head = init->addr - base;
if (head != prev + 4 || xfer >= 32) {
if (xfer) {
u32 data = ((--xfer << 26) | addr);
- nv_wr32(priv, falcon + 0x01c4, data);
+ nv_wr32(gr, falcon + 0x01c4, data);
star += 4;
}
addr = head;
}
}
- nv_wr32(priv, falcon + 0x01c4, (--xfer << 26) | addr);
- nv_wr32(priv, falcon + 0x01c0, 0x01000004 + starstar);
- nv_wr32(priv, falcon + 0x01c4, star + 4);
+ nv_wr32(gr, falcon + 0x01c4, (--xfer << 26) | addr);
+ nv_wr32(gr, falcon + 0x01c0, 0x01000004 + starstar);
+ nv_wr32(gr, falcon + 0x01c4, star + 4);
}
int
-gf100_gr_init_ctxctl(struct gf100_gr_priv *priv)
+gf100_gr_init_ctxctl(struct gf100_gr *gr)
{
- struct gf100_gr_oclass *oclass = (void *)nv_object(priv)->oclass;
- struct gf100_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_gr_oclass *oclass = (void *)nv_object(gr)->oclass;
+ struct gf100_grctx_oclass *cclass = (void *)nv_engine(gr)->cclass;
int i;
- if (priv->firmware) {
+ if (gr->firmware) {
/* load fuc microcode */
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
- gf100_gr_init_fw(priv, 0x409000, &priv->fuc409c,
- &priv->fuc409d);
- gf100_gr_init_fw(priv, 0x41a000, &priv->fuc41ac,
- &priv->fuc41ad);
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
+ gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c,
+ &gr->fuc409d);
+ gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac,
+ &gr->fuc41ad);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
/* start both of them running */
- nv_wr32(priv, 0x409840, 0xffffffff);
- nv_wr32(priv, 0x41a10c, 0x00000000);
- nv_wr32(priv, 0x40910c, 0x00000000);
- nv_wr32(priv, 0x41a100, 0x00000002);
- nv_wr32(priv, 0x409100, 0x00000002);
- if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001))
- nv_warn(priv, "0x409800 wait failed\n");
-
- nv_wr32(priv, 0x409840, 0xffffffff);
- nv_wr32(priv, 0x409500, 0x7fffffff);
- nv_wr32(priv, 0x409504, 0x00000021);
-
- nv_wr32(priv, 0x409840, 0xffffffff);
- nv_wr32(priv, 0x409500, 0x00000000);
- nv_wr32(priv, 0x409504, 0x00000010);
- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
- nv_error(priv, "fuc09 req 0x10 timeout\n");
+ nv_wr32(gr, 0x409840, 0xffffffff);
+ nv_wr32(gr, 0x41a10c, 0x00000000);
+ nv_wr32(gr, 0x40910c, 0x00000000);
+ nv_wr32(gr, 0x41a100, 0x00000002);
+ nv_wr32(gr, 0x409100, 0x00000002);
+ if (!nv_wait(gr, 0x409800, 0x00000001, 0x00000001))
+ nv_warn(gr, "0x409800 wait failed\n");
+
+ nv_wr32(gr, 0x409840, 0xffffffff);
+ nv_wr32(gr, 0x409500, 0x7fffffff);
+ nv_wr32(gr, 0x409504, 0x00000021);
+
+ nv_wr32(gr, 0x409840, 0xffffffff);
+ nv_wr32(gr, 0x409500, 0x00000000);
+ nv_wr32(gr, 0x409504, 0x00000010);
+ if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) {
+ nv_error(gr, "fuc09 req 0x10 timeout\n");
return -EBUSY;
}
- priv->size = nv_rd32(priv, 0x409800);
+ gr->size = nv_rd32(gr, 0x409800);
- nv_wr32(priv, 0x409840, 0xffffffff);
- nv_wr32(priv, 0x409500, 0x00000000);
- nv_wr32(priv, 0x409504, 0x00000016);
- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
- nv_error(priv, "fuc09 req 0x16 timeout\n");
+ nv_wr32(gr, 0x409840, 0xffffffff);
+ nv_wr32(gr, 0x409500, 0x00000000);
+ nv_wr32(gr, 0x409504, 0x00000016);
+ if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) {
+ nv_error(gr, "fuc09 req 0x16 timeout\n");
return -EBUSY;
}
- nv_wr32(priv, 0x409840, 0xffffffff);
- nv_wr32(priv, 0x409500, 0x00000000);
- nv_wr32(priv, 0x409504, 0x00000025);
- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
- nv_error(priv, "fuc09 req 0x25 timeout\n");
+ nv_wr32(gr, 0x409840, 0xffffffff);
+ nv_wr32(gr, 0x409500, 0x00000000);
+ nv_wr32(gr, 0x409504, 0x00000025);
+ if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) {
+ nv_error(gr, "fuc09 req 0x25 timeout\n");
return -EBUSY;
}
- if (nv_device(priv)->chipset >= 0xe0) {
- nv_wr32(priv, 0x409800, 0x00000000);
- nv_wr32(priv, 0x409500, 0x00000001);
- nv_wr32(priv, 0x409504, 0x00000030);
- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
- nv_error(priv, "fuc09 req 0x30 timeout\n");
+ if (nv_device(gr)->chipset >= 0xe0) {
+ nv_wr32(gr, 0x409800, 0x00000000);
+ nv_wr32(gr, 0x409500, 0x00000001);
+ nv_wr32(gr, 0x409504, 0x00000030);
+ if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) {
+ nv_error(gr, "fuc09 req 0x30 timeout\n");
return -EBUSY;
}
- nv_wr32(priv, 0x409810, 0xb00095c8);
- nv_wr32(priv, 0x409800, 0x00000000);
- nv_wr32(priv, 0x409500, 0x00000001);
- nv_wr32(priv, 0x409504, 0x00000031);
- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
- nv_error(priv, "fuc09 req 0x31 timeout\n");
+ nv_wr32(gr, 0x409810, 0xb00095c8);
+ nv_wr32(gr, 0x409800, 0x00000000);
+ nv_wr32(gr, 0x409500, 0x00000001);
+ nv_wr32(gr, 0x409504, 0x00000031);
+ if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) {
+ nv_error(gr, "fuc09 req 0x31 timeout\n");
return -EBUSY;
}
- nv_wr32(priv, 0x409810, 0x00080420);
- nv_wr32(priv, 0x409800, 0x00000000);
- nv_wr32(priv, 0x409500, 0x00000001);
- nv_wr32(priv, 0x409504, 0x00000032);
- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
- nv_error(priv, "fuc09 req 0x32 timeout\n");
+ nv_wr32(gr, 0x409810, 0x00080420);
+ nv_wr32(gr, 0x409800, 0x00000000);
+ nv_wr32(gr, 0x409500, 0x00000001);
+ nv_wr32(gr, 0x409504, 0x00000032);
+ if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) {
+ nv_error(gr, "fuc09 req 0x32 timeout\n");
return -EBUSY;
}
- nv_wr32(priv, 0x409614, 0x00000070);
- nv_wr32(priv, 0x409614, 0x00000770);
- nv_wr32(priv, 0x40802c, 0x00000001);
+ nv_wr32(gr, 0x409614, 0x00000070);
+ nv_wr32(gr, 0x409614, 0x00000770);
+ nv_wr32(gr, 0x40802c, 0x00000001);
}
- if (priv->data == NULL) {
- int ret = gf100_grctx_generate(priv);
+ if (gr->data == NULL) {
+ int ret = gf100_grctx_generate(gr);
if (ret) {
- nv_error(priv, "failed to construct context\n");
+ nv_error(gr, "failed to construct context\n");
return ret;
}
}
}
/* load HUB microcode */
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
- nv_wr32(priv, 0x4091c0, 0x01000000);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
+ nv_wr32(gr, 0x4091c0, 0x01000000);
for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++)
- nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]);
+ nv_wr32(gr, 0x4091c4, oclass->fecs.ucode->data.data[i]);
- nv_wr32(priv, 0x409180, 0x01000000);
+ nv_wr32(gr, 0x409180, 0x01000000);
for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) {
if ((i & 0x3f) == 0)
- nv_wr32(priv, 0x409188, i >> 6);
- nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]);
+ nv_wr32(gr, 0x409188, i >> 6);
+ nv_wr32(gr, 0x409184, oclass->fecs.ucode->code.data[i]);
}
/* load GPC microcode */
- nv_wr32(priv, 0x41a1c0, 0x01000000);
+ nv_wr32(gr, 0x41a1c0, 0x01000000);
for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++)
- nv_wr32(priv, 0x41a1c4, oclass->gpccs.ucode->data.data[i]);
+ nv_wr32(gr, 0x41a1c4, oclass->gpccs.ucode->data.data[i]);
- nv_wr32(priv, 0x41a180, 0x01000000);
+ nv_wr32(gr, 0x41a180, 0x01000000);
for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) {
if ((i & 0x3f) == 0)
- nv_wr32(priv, 0x41a188, i >> 6);
- nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]);
+ nv_wr32(gr, 0x41a188, i >> 6);
+ nv_wr32(gr, 0x41a184, oclass->gpccs.ucode->code.data[i]);
}
- nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
+ nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
/* load register lists */
- gf100_gr_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000);
- gf100_gr_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000);
- gf100_gr_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800);
- gf100_gr_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00);
+ gf100_gr_init_csdata(gr, cclass->hub, 0x409000, 0x000, 0x000000);
+ gf100_gr_init_csdata(gr, cclass->gpc, 0x41a000, 0x000, 0x418000);
+ gf100_gr_init_csdata(gr, cclass->tpc, 0x41a000, 0x004, 0x419800);
+ gf100_gr_init_csdata(gr, cclass->ppc, 0x41a000, 0x008, 0x41be00);
/* start HUB ucode running, it'll init the GPCs */
- nv_wr32(priv, 0x40910c, 0x00000000);
- nv_wr32(priv, 0x409100, 0x00000002);
- if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
- nv_error(priv, "HUB_INIT timed out\n");
- gf100_gr_ctxctl_debug(priv);
+ nv_wr32(gr, 0x40910c, 0x00000000);
+ nv_wr32(gr, 0x409100, 0x00000002);
+ if (!nv_wait(gr, 0x409800, 0x80000000, 0x80000000)) {
+ nv_error(gr, "HUB_INIT timed out\n");
+ gf100_gr_ctxctl_debug(gr);
return -EBUSY;
}
- priv->size = nv_rd32(priv, 0x409804);
- if (priv->data == NULL) {
- int ret = gf100_grctx_generate(priv);
+ gr->size = nv_rd32(gr, 0x409804);
+ if (gr->data == NULL) {
+ int ret = gf100_grctx_generate(gr);
if (ret) {
- nv_error(priv, "failed to construct context\n");
+ nv_error(gr, "failed to construct context\n");
return ret;
}
}
gf100_gr_init(struct nvkm_object *object)
{
struct gf100_gr_oclass *oclass = (void *)object->oclass;
- struct gf100_gr_priv *priv = (void *)object;
- const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
+ struct gf100_gr *gr = (void *)object;
+ const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, rop;
int ret, i;
- ret = nvkm_gr_init(&priv->base);
+ ret = nvkm_gr_init(&gr->base);
if (ret)
return ret;
- nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
- nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
+ nv_wr32(gr, GPC_BCAST(0x0880), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x08a4), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x0888), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x088c), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x0890), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x0894), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8);
+ nv_wr32(gr, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8);
- gf100_gr_mmio(priv, oclass->mmio);
+ gf100_gr_mmio(gr, oclass->mmio);
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
- for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
+ for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
+ tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
data[i / 8] |= tpc << ((i % 8) * 4);
}
- nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
- nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
- nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
- nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
+ nv_wr32(gr, GPC_BCAST(0x0980), data[0]);
+ nv_wr32(gr, GPC_BCAST(0x0984), data[1]);
+ nv_wr32(gr, GPC_BCAST(0x0988), data[2]);
+ nv_wr32(gr, GPC_BCAST(0x098c), data[3]);
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
- priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
- priv->tpc_total);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0914),
+ gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 |
+ gr->tpc_total);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
- if (nv_device(priv)->chipset != 0xd7)
- nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918);
+ if (nv_device(gr)->chipset != 0xd7)
+ nv_wr32(gr, GPC_BCAST(0x1bd4), magicgpc918);
else
- nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
-
- nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
-
- nv_wr32(priv, 0x400500, 0x00010001);
-
- nv_wr32(priv, 0x400100, 0xffffffff);
- nv_wr32(priv, 0x40013c, 0xffffffff);
-
- nv_wr32(priv, 0x409c24, 0x000f0000);
- nv_wr32(priv, 0x404000, 0xc0000000);
- nv_wr32(priv, 0x404600, 0xc0000000);
- nv_wr32(priv, 0x408030, 0xc0000000);
- nv_wr32(priv, 0x40601c, 0xc0000000);
- nv_wr32(priv, 0x404490, 0xc0000000);
- nv_wr32(priv, 0x406018, 0xc0000000);
- nv_wr32(priv, 0x405840, 0xc0000000);
- nv_wr32(priv, 0x405844, 0x00ffffff);
- nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
- nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
-
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
+ nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918);
+
+ nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800));
+
+ nv_wr32(gr, 0x400500, 0x00010001);
+
+ nv_wr32(gr, 0x400100, 0xffffffff);
+ nv_wr32(gr, 0x40013c, 0xffffffff);
+
+ nv_wr32(gr, 0x409c24, 0x000f0000);
+ nv_wr32(gr, 0x404000, 0xc0000000);
+ nv_wr32(gr, 0x404600, 0xc0000000);
+ nv_wr32(gr, 0x408030, 0xc0000000);
+ nv_wr32(gr, 0x40601c, 0xc0000000);
+ nv_wr32(gr, 0x404490, 0xc0000000);
+ nv_wr32(gr, 0x406018, 0xc0000000);
+ nv_wr32(gr, 0x405840, 0xc0000000);
+ nv_wr32(gr, 0x405844, 0x00ffffff);
+ nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008);
+ nv_mask(gr, 0x419eb4, 0x00001000, 0x00001000);
+
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000);
+ for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
}
- nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
- nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
}
- for (rop = 0; rop < priv->rop_nr; rop++) {
- nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
- nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
- nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
- nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
+ for (rop = 0; rop < gr->rop_nr; rop++) {
+ nv_wr32(gr, ROP_UNIT(rop, 0x144), 0xc0000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x070), 0xc0000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff);
+ nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff);
}
- nv_wr32(priv, 0x400108, 0xffffffff);
- nv_wr32(priv, 0x400138, 0xffffffff);
- nv_wr32(priv, 0x400118, 0xffffffff);
- nv_wr32(priv, 0x400130, 0xffffffff);
- nv_wr32(priv, 0x40011c, 0xffffffff);
- nv_wr32(priv, 0x400134, 0xffffffff);
+ nv_wr32(gr, 0x400108, 0xffffffff);
+ nv_wr32(gr, 0x400138, 0xffffffff);
+ nv_wr32(gr, 0x400118, 0xffffffff);
+ nv_wr32(gr, 0x400130, 0xffffffff);
+ nv_wr32(gr, 0x40011c, 0xffffffff);
+ nv_wr32(gr, 0x400134, 0xffffffff);
- nv_wr32(priv, 0x400054, 0x34ce3464);
+ nv_wr32(gr, 0x400054, 0x34ce3464);
- gf100_gr_zbc_init(priv);
+ gf100_gr_zbc_init(gr);
- return gf100_gr_init_ctxctl(priv);
+ return gf100_gr_init_ctxctl(gr);
}
void
}
int
-gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname,
+gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname,
struct gf100_gr_fuc *fuc)
{
- struct nvkm_device *device = nv_device(priv);
+ struct nvkm_device *device = nv_device(gr);
const struct firmware *fw;
char f[64];
char cname[16];
snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname);
ret = request_firmware(&fw, f, nv_device_base(device));
if (ret) {
- nv_error(priv, "failed to load %s\n", fwname);
+ nv_error(gr, "failed to load %s\n", fwname);
return ret;
}
void
gf100_gr_dtor(struct nvkm_object *object)
{
- struct gf100_gr_priv *priv = (void *)object;
+ struct gf100_gr *gr = (void *)object;
- kfree(priv->data);
+ kfree(gr->data);
- gf100_gr_dtor_fw(&priv->fuc409c);
- gf100_gr_dtor_fw(&priv->fuc409d);
- gf100_gr_dtor_fw(&priv->fuc41ac);
- gf100_gr_dtor_fw(&priv->fuc41ad);
+ gf100_gr_dtor_fw(&gr->fuc409c);
+ gf100_gr_dtor_fw(&gr->fuc409d);
+ gf100_gr_dtor_fw(&gr->fuc41ac);
+ gf100_gr_dtor_fw(&gr->fuc41ad);
- nvkm_gpuobj_ref(NULL, &priv->unk4188b8);
- nvkm_gpuobj_ref(NULL, &priv->unk4188b4);
+ nvkm_gpuobj_ref(NULL, &gr->unk4188b8);
+ nvkm_gpuobj_ref(NULL, &gr->unk4188b4);
- nvkm_gr_destroy(&priv->base);
+ nvkm_gr_destroy(&gr->base);
}
int
{
struct gf100_gr_oclass *oclass = (void *)bclass;
struct nvkm_device *device = nv_device(parent);
- struct gf100_gr_priv *priv;
+ struct gf100_gr *gr;
bool use_ext_fw, enable;
int ret, i, j;
oclass->fecs.ucode == NULL);
enable = use_ext_fw || oclass->fecs.ucode != NULL;
- ret = nvkm_gr_create(parent, engine, bclass, enable, &priv);
- *pobject = nv_object(priv);
+ ret = nvkm_gr_create(parent, engine, bclass, enable, &gr);
+ *pobject = nv_object(gr);
if (ret)
return ret;
- nv_subdev(priv)->unit = 0x08001000;
- nv_subdev(priv)->intr = gf100_gr_intr;
+ nv_subdev(gr)->unit = 0x08001000;
+ nv_subdev(gr)->intr = gf100_gr_intr;
- priv->base.units = gf100_gr_units;
+ gr->base.units = gf100_gr_units;
if (use_ext_fw) {
- nv_info(priv, "using external firmware\n");
- if (gf100_gr_ctor_fw(priv, "fecs_inst", &priv->fuc409c) ||
- gf100_gr_ctor_fw(priv, "fecs_data", &priv->fuc409d) ||
- gf100_gr_ctor_fw(priv, "gpccs_inst", &priv->fuc41ac) ||
- gf100_gr_ctor_fw(priv, "gpccs_data", &priv->fuc41ad))
+ nv_info(gr, "using external firmware\n");
+ if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) ||
+ gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) ||
+ gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) ||
+ gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad))
return -ENODEV;
- priv->firmware = true;
+ gr->firmware = true;
}
- ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
- &priv->unk4188b4);
+ ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0,
+ &gr->unk4188b4);
if (ret)
return ret;
- ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
- &priv->unk4188b8);
+ ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0,
+ &gr->unk4188b8);
if (ret)
return ret;
for (i = 0; i < 0x1000; i += 4) {
- nv_wo32(priv->unk4188b4, i, 0x00000010);
- nv_wo32(priv->unk4188b8, i, 0x00000010);
- }
-
- priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16;
- priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f;
- for (i = 0; i < priv->gpc_nr; i++) {
- priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608));
- priv->tpc_total += priv->tpc_nr[i];
- priv->ppc_nr[i] = oclass->ppc_nr;
- for (j = 0; j < priv->ppc_nr[i]; j++) {
- u8 mask = nv_rd32(priv, GPC_UNIT(i, 0x0c30 + (j * 4)));
- priv->ppc_tpc_nr[i][j] = hweight8(mask);
+ nv_wo32(gr->unk4188b4, i, 0x00000010);
+ nv_wo32(gr->unk4188b8, i, 0x00000010);
+ }
+
+ gr->rop_nr = (nv_rd32(gr, 0x409604) & 0x001f0000) >> 16;
+ gr->gpc_nr = nv_rd32(gr, 0x409604) & 0x0000001f;
+ for (i = 0; i < gr->gpc_nr; i++) {
+ gr->tpc_nr[i] = nv_rd32(gr, GPC_UNIT(i, 0x2608));
+ gr->tpc_total += gr->tpc_nr[i];
+ gr->ppc_nr[i] = oclass->ppc_nr;
+ for (j = 0; j < gr->ppc_nr[i]; j++) {
+ u8 mask = nv_rd32(gr, GPC_UNIT(i, 0x0c30 + (j * 4)));
+ gr->ppc_tpc_nr[i][j] = hweight8(mask);
}
}
/*XXX: these need figuring out... though it might not even matter */
- switch (nv_device(priv)->chipset) {
+ switch (nv_device(gr)->chipset) {
case 0xc0:
- if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
- priv->magic_not_rop_nr = 0x07;
+ if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
+ gr->magic_not_rop_nr = 0x07;
} else
- if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
- priv->magic_not_rop_nr = 0x05;
+ if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
+ gr->magic_not_rop_nr = 0x05;
} else
- if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
- priv->magic_not_rop_nr = 0x06;
+ if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
+ gr->magic_not_rop_nr = 0x06;
}
break;
case 0xc3: /* 450, 4/0/0/0, 2 */
- priv->magic_not_rop_nr = 0x03;
+ gr->magic_not_rop_nr = 0x03;
break;
case 0xc4: /* 460, 3/4/0/0, 4 */
- priv->magic_not_rop_nr = 0x01;
+ gr->magic_not_rop_nr = 0x01;
break;
case 0xc1: /* 2/0/0/0, 1 */
- priv->magic_not_rop_nr = 0x01;
+ gr->magic_not_rop_nr = 0x01;
break;
case 0xc8: /* 4/4/3/4, 5 */
- priv->magic_not_rop_nr = 0x06;
+ gr->magic_not_rop_nr = 0x06;
break;
case 0xce: /* 4/4/0/0, 4 */
- priv->magic_not_rop_nr = 0x03;
+ gr->magic_not_rop_nr = 0x03;
break;
case 0xcf: /* 4/0/0/0, 3 */
- priv->magic_not_rop_nr = 0x03;
+ gr->magic_not_rop_nr = 0x03;
break;
case 0xd7:
case 0xd9: /* 1/0/0/0, 1 */
case 0xea: /* gk20a */
case 0x12b: /* gm20b */
- priv->magic_not_rop_nr = 0x01;
+ gr->magic_not_rop_nr = 0x01;
break;
}
- nv_engine(priv)->cclass = *oclass->cclass;
- nv_engine(priv)->sclass = oclass->sclass;
+ nv_engine(gr)->cclass = *oclass->cclass;
+ nv_engine(gr)->sclass = oclass->sclass;
return 0;
}
u32 l2;
};
-struct gf100_gr_priv {
+struct gf100_gr {
struct nvkm_gr base;
struct gf100_gr_fuc fuc409c;
struct nvkm_object **);
void gf100_gr_context_dtor(struct nvkm_object *);
-void gf100_gr_ctxctl_debug(struct gf100_gr_priv *);
+void gf100_gr_ctxctl_debug(struct gf100_gr *);
void gf100_gr_dtor_fw(struct gf100_gr_fuc *);
-int gf100_gr_ctor_fw(struct gf100_gr_priv *, const char *,
+int gf100_gr_ctor_fw(struct gf100_gr *, const char *,
struct gf100_gr_fuc *);
u64 gf100_gr_units(struct nvkm_gr *);
int gf100_gr_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_object **);
void gf100_gr_dtor(struct nvkm_object *);
int gf100_gr_init(struct nvkm_object *);
-void gf100_gr_zbc_init(struct gf100_gr_priv *);
+void gf100_gr_zbc_init(struct gf100_gr *);
int gk104_gr_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *data, u32 size,
int ppc_nr;
};
-int gf100_gr_wait_idle(struct gf100_gr_priv *);
-void gf100_gr_mmio(struct gf100_gr_priv *, const struct gf100_gr_pack *);
-void gf100_gr_icmd(struct gf100_gr_priv *, const struct gf100_gr_pack *);
-void gf100_gr_mthd(struct gf100_gr_priv *, const struct gf100_gr_pack *);
-int gf100_gr_init_ctxctl(struct gf100_gr_priv *);
+int gf100_gr_wait_idle(struct gf100_gr *);
+void gf100_gr_mmio(struct gf100_gr *, const struct gf100_gr_pack *);
+void gf100_gr_icmd(struct gf100_gr *, const struct gf100_gr_pack *);
+void gf100_gr_mthd(struct gf100_gr *, const struct gf100_gr_pack *);
+int gf100_gr_init_ctxctl(struct gf100_gr *);
/* register init value lists */
extern const struct gf100_gr_init gm107_gr_init_l1c_0[];
extern const struct gf100_gr_init gm107_gr_init_wwdx_0[];
extern const struct gf100_gr_init gm107_gr_init_cbm_0[];
-void gm107_gr_init_bios(struct gf100_gr_priv *);
+void gm107_gr_init_bios(struct gf100_gr *);
extern const struct gf100_gr_pack gm204_gr_pack_mmio[];
#endif
gk104_gr_init(struct nvkm_object *object)
{
struct gf100_gr_oclass *oclass = (void *)object->oclass;
- struct gf100_gr_priv *priv = (void *)object;
- struct nvkm_pmu *pmu = nvkm_pmu(priv);
- const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
+ struct gf100_gr *gr = (void *)object;
+ struct nvkm_pmu *pmu = nvkm_pmu(gr);
+ const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, rop;
if (pmu)
pmu->pgob(pmu, false);
- ret = nvkm_gr_init(&priv->base);
+ ret = nvkm_gr_init(&gr->base);
if (ret)
return ret;
- nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000);
- nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
- nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
+ nv_wr32(gr, GPC_BCAST(0x0880), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x08a4), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x0888), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x088c), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x0890), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x0894), 0x00000000);
+ nv_wr32(gr, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8);
+ nv_wr32(gr, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8);
- gf100_gr_mmio(priv, oclass->mmio);
+ gf100_gr_mmio(gr, oclass->mmio);
- nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
+ nv_wr32(gr, GPC_UNIT(0, 0x3018), 0x00000001);
memset(data, 0x00, sizeof(data));
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
- for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
+ for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
+ tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
data[i / 8] |= tpc << ((i % 8) * 4);
}
- nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
- nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
- nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
- nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
-
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
- priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
- priv->tpc_total);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
+ nv_wr32(gr, GPC_BCAST(0x0980), data[0]);
+ nv_wr32(gr, GPC_BCAST(0x0984), data[1]);
+ nv_wr32(gr, GPC_BCAST(0x0988), data[2]);
+ nv_wr32(gr, GPC_BCAST(0x098c), data[3]);
+
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0914),
+ gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 |
+ gr->tpc_total);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
- nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
- nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
-
- nv_wr32(priv, 0x400500, 0x00010001);
-
- nv_wr32(priv, 0x400100, 0xffffffff);
- nv_wr32(priv, 0x40013c, 0xffffffff);
-
- nv_wr32(priv, 0x409ffc, 0x00000000);
- nv_wr32(priv, 0x409c14, 0x00003e3e);
- nv_wr32(priv, 0x409c24, 0x000f0001);
- nv_wr32(priv, 0x404000, 0xc0000000);
- nv_wr32(priv, 0x404600, 0xc0000000);
- nv_wr32(priv, 0x408030, 0xc0000000);
- nv_wr32(priv, 0x404490, 0xc0000000);
- nv_wr32(priv, 0x406018, 0xc0000000);
- nv_wr32(priv, 0x407020, 0x40000000);
- nv_wr32(priv, 0x405840, 0xc0000000);
- nv_wr32(priv, 0x405844, 0x00ffffff);
- nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
- nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
-
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
+ nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918);
+ nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800));
+
+ nv_wr32(gr, 0x400500, 0x00010001);
+
+ nv_wr32(gr, 0x400100, 0xffffffff);
+ nv_wr32(gr, 0x40013c, 0xffffffff);
+
+ nv_wr32(gr, 0x409ffc, 0x00000000);
+ nv_wr32(gr, 0x409c14, 0x00003e3e);
+ nv_wr32(gr, 0x409c24, 0x000f0001);
+ nv_wr32(gr, 0x404000, 0xc0000000);
+ nv_wr32(gr, 0x404600, 0xc0000000);
+ nv_wr32(gr, 0x408030, 0xc0000000);
+ nv_wr32(gr, 0x404490, 0xc0000000);
+ nv_wr32(gr, 0x406018, 0xc0000000);
+ nv_wr32(gr, 0x407020, 0x40000000);
+ nv_wr32(gr, 0x405840, 0xc0000000);
+ nv_wr32(gr, 0x405844, 0x00ffffff);
+ nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008);
+ nv_mask(gr, 0x419eb4, 0x00001000, 0x00001000);
+
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ nv_wr32(gr, GPC_UNIT(gpc, 0x3038), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000);
+ for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
+ nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
}
- nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
- nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
}
- for (rop = 0; rop < priv->rop_nr; rop++) {
- nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
- nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
- nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
- nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
+ for (rop = 0; rop < gr->rop_nr; rop++) {
+ nv_wr32(gr, ROP_UNIT(rop, 0x144), 0xc0000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x070), 0xc0000000);
+ nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff);
+ nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff);
}
- nv_wr32(priv, 0x400108, 0xffffffff);
- nv_wr32(priv, 0x400138, 0xffffffff);
- nv_wr32(priv, 0x400118, 0xffffffff);
- nv_wr32(priv, 0x400130, 0xffffffff);
- nv_wr32(priv, 0x40011c, 0xffffffff);
- nv_wr32(priv, 0x400134, 0xffffffff);
+ nv_wr32(gr, 0x400108, 0xffffffff);
+ nv_wr32(gr, 0x400138, 0xffffffff);
+ nv_wr32(gr, 0x400118, 0xffffffff);
+ nv_wr32(gr, 0x400130, 0xffffffff);
+ nv_wr32(gr, 0x40011c, 0xffffffff);
+ nv_wr32(gr, 0x400134, 0xffffffff);
- nv_wr32(priv, 0x400054, 0x34ce3464);
+ nv_wr32(gr, 0x400054, 0x34ce3464);
- gf100_gr_zbc_init(priv);
+ gf100_gr_zbc_init(gr);
- return gf100_gr_init_ctxctl(priv);
+ return gf100_gr_init_ctxctl(gr);
}
int
struct nvkm_object **pobject)
{
int err;
- struct gf100_gr_priv *priv;
+ struct gf100_gr *gr;
struct gf100_gr_fuc fuc;
err = gf100_gr_ctor(parent, engine, oclass, data, size, pobject);
if (err)
return err;
- priv = (void *)*pobject;
+ gr = (void *)*pobject;
- err = gf100_gr_ctor_fw(priv, "sw_nonctx", &fuc);
+ err = gf100_gr_ctor_fw(gr, "sw_nonctx", &fuc);
if (err)
return err;
- priv->fuc_sw_nonctx = gk20a_gr_av_to_init(&fuc);
+ gr->fuc_sw_nonctx = gk20a_gr_av_to_init(&fuc);
gf100_gr_dtor_fw(&fuc);
- if (IS_ERR(priv->fuc_sw_nonctx))
- return PTR_ERR(priv->fuc_sw_nonctx);
+ if (IS_ERR(gr->fuc_sw_nonctx))
+ return PTR_ERR(gr->fuc_sw_nonctx);
- err = gf100_gr_ctor_fw(priv, "sw_ctx", &fuc);
+ err = gf100_gr_ctor_fw(gr, "sw_ctx", &fuc);
if (err)
return err;
- priv->fuc_sw_ctx = gk20a_gr_aiv_to_init(&fuc);
+ gr->fuc_sw_ctx = gk20a_gr_aiv_to_init(&fuc);
gf100_gr_dtor_fw(&fuc);
- if (IS_ERR(priv->fuc_sw_ctx))
- return PTR_ERR(priv->fuc_sw_ctx);
+ if (IS_ERR(gr->fuc_sw_ctx))
+ return PTR_ERR(gr->fuc_sw_ctx);
- err = gf100_gr_ctor_fw(priv, "sw_bundle_init", &fuc);
+ err = gf100_gr_ctor_fw(gr, "sw_bundle_init", &fuc);
if (err)
return err;
- priv->fuc_bundle = gk20a_gr_av_to_init(&fuc);
+ gr->fuc_bundle = gk20a_gr_av_to_init(&fuc);
gf100_gr_dtor_fw(&fuc);
- if (IS_ERR(priv->fuc_bundle))
- return PTR_ERR(priv->fuc_bundle);
+ if (IS_ERR(gr->fuc_bundle))
+ return PTR_ERR(gr->fuc_bundle);
- err = gf100_gr_ctor_fw(priv, "sw_method_init", &fuc);
+ err = gf100_gr_ctor_fw(gr, "sw_method_init", &fuc);
if (err)
return err;
- priv->fuc_method = gk20a_gr_av_to_method(&fuc);
+ gr->fuc_method = gk20a_gr_av_to_method(&fuc);
gf100_gr_dtor_fw(&fuc);
- if (IS_ERR(priv->fuc_method))
- return PTR_ERR(priv->fuc_method);
+ if (IS_ERR(gr->fuc_method))
+ return PTR_ERR(gr->fuc_method);
return 0;
}
void
gk20a_gr_dtor(struct nvkm_object *object)
{
- struct gf100_gr_priv *priv = (void *)object;
+ struct gf100_gr *gr = (void *)object;
- gk20a_gr_init_dtor(priv->fuc_method);
- gk20a_gr_init_dtor(priv->fuc_bundle);
- gk20a_gr_init_dtor(priv->fuc_sw_ctx);
- gk20a_gr_init_dtor(priv->fuc_sw_nonctx);
+ gk20a_gr_init_dtor(gr->fuc_method);
+ gk20a_gr_init_dtor(gr->fuc_bundle);
+ gk20a_gr_init_dtor(gr->fuc_sw_ctx);
+ gk20a_gr_init_dtor(gr->fuc_sw_nonctx);
gf100_gr_dtor(object);
}
static int
-gk20a_gr_wait_mem_scrubbing(struct gf100_gr_priv *priv)
+gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
{
- if (!nv_wait(priv, 0x40910c, 0x6, 0x0)) {
- nv_error(priv, "FECS mem scrubbing timeout\n");
+ if (!nv_wait(gr, 0x40910c, 0x6, 0x0)) {
+ nv_error(gr, "FECS mem scrubbing timeout\n");
return -ETIMEDOUT;
}
- if (!nv_wait(priv, 0x41a10c, 0x6, 0x0)) {
- nv_error(priv, "GPCCS mem scrubbing timeout\n");
+ if (!nv_wait(gr, 0x41a10c, 0x6, 0x0)) {
+ nv_error(gr, "GPCCS mem scrubbing timeout\n");
return -ETIMEDOUT;
}
}
static void
-gk20a_gr_set_hww_esr_report_mask(struct gf100_gr_priv *priv)
+gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
{
- nv_wr32(priv, 0x419e44, 0x1ffffe);
- nv_wr32(priv, 0x419e4c, 0x7f);
+ nv_wr32(gr, 0x419e44, 0x1ffffe);
+ nv_wr32(gr, 0x419e4c, 0x7f);
}
int
gk20a_gr_init(struct nvkm_object *object)
{
struct gk20a_gr_oclass *oclass = (void *)object->oclass;
- struct gf100_gr_priv *priv = (void *)object;
- const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
+ struct gf100_gr *gr = (void *)object;
+ const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc;
int ret, i;
- ret = nvkm_gr_init(&priv->base);
+ ret = nvkm_gr_init(&gr->base);
if (ret)
return ret;
/* Clear SCC RAM */
- nv_wr32(priv, 0x40802c, 0x1);
+ nv_wr32(gr, 0x40802c, 0x1);
- gf100_gr_mmio(priv, priv->fuc_sw_nonctx);
+ gf100_gr_mmio(gr, gr->fuc_sw_nonctx);
- ret = gk20a_gr_wait_mem_scrubbing(priv);
+ ret = gk20a_gr_wait_mem_scrubbing(gr);
if (ret)
return ret;
- ret = gf100_gr_wait_idle(priv);
+ ret = gf100_gr_wait_idle(gr);
if (ret)
return ret;
/* MMU debug buffer */
- nv_wr32(priv, 0x100cc8, priv->unk4188b4->addr >> 8);
- nv_wr32(priv, 0x100ccc, priv->unk4188b8->addr >> 8);
+ nv_wr32(gr, 0x100cc8, gr->unk4188b4->addr >> 8);
+ nv_wr32(gr, 0x100ccc, gr->unk4188b8->addr >> 8);
if (oclass->init_gpc_mmu)
- oclass->init_gpc_mmu(priv);
+ oclass->init_gpc_mmu(gr);
/* Set the PE as stream master */
- nv_mask(priv, 0x503018, 0x1, 0x1);
+ nv_mask(gr, 0x503018, 0x1, 0x1);
/* Zcull init */
memset(data, 0x00, sizeof(data));
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
- for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
+ for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
+ tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
data[i / 8] |= tpc << ((i % 8) * 4);
}
- nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
- nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
- nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
- nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
-
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
- priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
- priv->tpc_total);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
+ nv_wr32(gr, GPC_BCAST(0x0980), data[0]);
+ nv_wr32(gr, GPC_BCAST(0x0984), data[1]);
+ nv_wr32(gr, GPC_BCAST(0x0988), data[2]);
+ nv_wr32(gr, GPC_BCAST(0x098c), data[3]);
+
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0914),
+ gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 |
+ gr->tpc_total);
+ nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
- nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
+ nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918);
/* Enable FIFO access */
- nv_wr32(priv, 0x400500, 0x00010001);
+ nv_wr32(gr, 0x400500, 0x00010001);
/* Enable interrupts */
- nv_wr32(priv, 0x400100, 0xffffffff);
- nv_wr32(priv, 0x40013c, 0xffffffff);
+ nv_wr32(gr, 0x400100, 0xffffffff);
+ nv_wr32(gr, 0x40013c, 0xffffffff);
/* Enable FECS error interrupts */
- nv_wr32(priv, 0x409c24, 0x000f0000);
+ nv_wr32(gr, 0x409c24, 0x000f0000);
/* Enable hardware warning exceptions */
- nv_wr32(priv, 0x404000, 0xc0000000);
- nv_wr32(priv, 0x404600, 0xc0000000);
+ nv_wr32(gr, 0x404000, 0xc0000000);
+ nv_wr32(gr, 0x404600, 0xc0000000);
if (oclass->set_hww_esr_report_mask)
- oclass->set_hww_esr_report_mask(priv);
+ oclass->set_hww_esr_report_mask(gr);
/* Enable TPC exceptions per GPC */
- nv_wr32(priv, 0x419d0c, 0x2);
- nv_wr32(priv, 0x41ac94, (((1 << priv->tpc_total) - 1) & 0xff) << 16);
+ nv_wr32(gr, 0x419d0c, 0x2);
+ nv_wr32(gr, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16);
/* Reset and enable all exceptions */
- nv_wr32(priv, 0x400108, 0xffffffff);
- nv_wr32(priv, 0x400138, 0xffffffff);
- nv_wr32(priv, 0x400118, 0xffffffff);
- nv_wr32(priv, 0x400130, 0xffffffff);
- nv_wr32(priv, 0x40011c, 0xffffffff);
- nv_wr32(priv, 0x400134, 0xffffffff);
+ nv_wr32(gr, 0x400108, 0xffffffff);
+ nv_wr32(gr, 0x400138, 0xffffffff);
+ nv_wr32(gr, 0x400118, 0xffffffff);
+ nv_wr32(gr, 0x400130, 0xffffffff);
+ nv_wr32(gr, 0x40011c, 0xffffffff);
+ nv_wr32(gr, 0x400134, 0xffffffff);
- gf100_gr_zbc_init(priv);
+ gf100_gr_zbc_init(gr);
- return gf100_gr_init_ctxctl(priv);
+ return gf100_gr_init_ctxctl(gr);
}
struct nvkm_oclass *
git.openpandora.org / pandora-kernel.git / commitdiff