.set_parent = imx8m_clk_mux_set_parent,
};
-struct clk *imx8m_clk_composite_flags(const char *name,
+struct clk *imx8m_clk_composite_flags(struct udevice *dev, const char *name,
const char * const *parent_names,
int num_parents, void __iomem *reg,
unsigned long flags)
gate->reg = reg;
gate->bit_idx = PCG_CGC_SHIFT;
- clk = clk_register_composite(NULL, name,
+ clk = clk_register_composite(dev, name,
parent_names, num_parents,
&mux->clk, &imx8m_clk_mux_ops, &div->clk,
&imx8m_clk_composite_divider_ops,
base + 0x8000, 0, 3));
clk_dm(IMX8MM_CLK_AHB,
- imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
+ imx8m_clk_composite_critical(dev, "ahb", imx8mm_ahb_sels,
base + 0x9000));
clk_dm(IMX8MM_CLK_IPG_ROOT,
imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
- imx8m_clk_composite_critical("nand_usdhc_bus",
+ imx8m_clk_composite_critical(dev, "nand_usdhc_bus",
imx8mm_nand_usdhc_sels,
base + 0x8900));
clk_dm(IMX8MM_CLK_USB_BUS,
- imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
+ imx8m_clk_composite(dev, "usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
/* IP */
#if CONFIG_IS_ENABLED(PCIE_DW_IMX)
clk_dm(IMX8MM_CLK_PCIE1_CTRL,
- imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
+ imx8m_clk_composite(dev, "pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
base + 0xa300));
clk_dm(IMX8MM_CLK_PCIE1_PHY,
- imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels,
+ imx8m_clk_composite(dev, "pcie1_phy", imx8mm_pcie1_phy_sels,
base + 0xa380));
clk_dm(IMX8MM_CLK_PCIE1_AUX,
- imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels,
+ imx8m_clk_composite(dev, "pcie1_aux", imx8mm_pcie1_aux_sels,
base + 0xa400));
#endif
clk_dm(IMX8MM_CLK_USDHC1,
- imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
+ imx8m_clk_composite(dev, "usdhc1", imx8mm_usdhc1_sels,
base + 0xac00));
clk_dm(IMX8MM_CLK_USDHC2,
- imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
+ imx8m_clk_composite(dev, "usdhc2", imx8mm_usdhc2_sels,
base + 0xac80));
clk_dm(IMX8MM_CLK_I2C1,
- imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
+ imx8m_clk_composite(dev, "i2c1", imx8mm_i2c1_sels, base + 0xad00));
clk_dm(IMX8MM_CLK_I2C2,
- imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
+ imx8m_clk_composite(dev, "i2c2", imx8mm_i2c2_sels, base + 0xad80));
clk_dm(IMX8MM_CLK_I2C3,
- imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
+ imx8m_clk_composite(dev, "i2c3", imx8mm_i2c3_sels, base + 0xae00));
clk_dm(IMX8MM_CLK_I2C4,
- imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
-
+ imx8m_clk_composite(dev, "i2c4", imx8mm_i2c4_sels, base + 0xae80));
clk_dm(IMX8MM_CLK_UART1,
- imx8m_clk_composite("uart1", imx8mm_uart1_sels, base + 0xaf00));
+ imx8m_clk_composite(dev, "uart1", imx8mm_uart1_sels, base + 0xaf00));
clk_dm(IMX8MM_CLK_UART2,
- imx8m_clk_composite("uart2", imx8mm_uart2_sels, base + 0xaf80));
+ imx8m_clk_composite(dev, "uart2", imx8mm_uart2_sels, base + 0xaf80));
clk_dm(IMX8MM_CLK_UART3,
- imx8m_clk_composite("uart3", imx8mm_uart3_sels, base + 0xb000));
+ imx8m_clk_composite(dev, "uart3", imx8mm_uart3_sels, base + 0xb000));
clk_dm(IMX8MM_CLK_UART4,
- imx8m_clk_composite("uart4", imx8mm_uart4_sels, base + 0xb080));
+ imx8m_clk_composite(dev, "uart4", imx8mm_uart4_sels, base + 0xb080));
clk_dm(IMX8MM_CLK_UART1_ROOT,
- imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
+ imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0));
clk_dm(IMX8MM_CLK_UART2_ROOT,
- imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
+ imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0));
clk_dm(IMX8MM_CLK_UART3_ROOT,
- imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
+ imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0));
clk_dm(IMX8MM_CLK_UART4_ROOT,
- imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
-
+ imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0));
clk_dm(IMX8MM_CLK_WDOG,
- imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
+ imx8m_clk_composite(dev, "wdog", imx8mm_wdog_sels, base + 0xb900));
clk_dm(IMX8MM_CLK_USDHC3,
- imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
+ imx8m_clk_composite(dev, "usdhc3", imx8mm_usdhc3_sels,
base + 0xbc80));
clk_dm(IMX8MM_CLK_USB_CORE_REF,
- imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
+ imx8m_clk_composite(dev, "usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
clk_dm(IMX8MM_CLK_USB_PHY_REF,
- imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
+ imx8m_clk_composite(dev, "usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
clk_dm(IMX8MM_CLK_I2C1_ROOT,
imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0));
clk_dm(IMX8MM_CLK_I2C2_ROOT,
/* clks not needed in SPL stage */
#ifndef CONFIG_XPL_BUILD
clk_dm(IMX8MM_CLK_ENET_AXI,
- imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
+ imx8m_clk_composite(dev, "enet_axi", imx8mm_enet_axi_sels,
base + 0x8880));
clk_dm(IMX8MM_CLK_ENET_REF,
- imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
+ imx8m_clk_composite(dev, "enet_ref", imx8mm_enet_ref_sels,
base + 0xa980));
clk_dm(IMX8MM_CLK_ENET_TIMER,
- imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels,
+ imx8m_clk_composite(dev, "enet_timer", imx8mm_enet_timer_sels,
base + 0xaa00));
clk_dm(IMX8MM_CLK_ENET_PHY_REF,
- imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels,
+ imx8m_clk_composite(dev, "enet_phy", imx8mm_enet_phy_sels,
base + 0xaa80));
clk_dm(IMX8MM_CLK_ENET1_ROOT,
imx_clk_gate4(dev, "enet1_root_clk", "enet_axi",
base + 0x40a0, 0));
clk_dm(IMX8MM_CLK_PWM1,
- imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380));
+ imx8m_clk_composite(dev, "pwm1", imx8mm_pwm1_sels, base + 0xb380));
clk_dm(IMX8MM_CLK_PWM2,
- imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400));
+ imx8m_clk_composite(dev, "pwm2", imx8mm_pwm2_sels, base + 0xb400));
clk_dm(IMX8MM_CLK_PWM3,
- imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480));
+ imx8m_clk_composite(dev, "pwm3", imx8mm_pwm3_sels, base + 0xb480));
clk_dm(IMX8MM_CLK_PWM4,
- imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500));
+ imx8m_clk_composite(dev, "pwm4", imx8mm_pwm4_sels, base + 0xb500));
clk_dm(IMX8MM_CLK_PWM1_ROOT,
imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0));
clk_dm(IMX8MM_CLK_PWM2_ROOT,
#if CONFIG_IS_ENABLED(DM_SPI)
clk_dm(IMX8MM_CLK_ECSPI1,
- imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
+ imx8m_clk_composite(dev, "ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
clk_dm(IMX8MM_CLK_ECSPI2,
- imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
+ imx8m_clk_composite(dev, "ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
clk_dm(IMX8MM_CLK_ECSPI3,
- imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
+ imx8m_clk_composite(dev, "ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
#if CONFIG_IS_ENABLED(NXP_FSPI)
clk_dm(IMX8MM_CLK_QSPI,
- imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
+ imx8m_clk_composite(dev, "qspi", imx8mm_qspi_sels, base + 0xab80));
clk_dm(IMX8MM_CLK_QSPI_ROOT,
imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0));
#endif
base + 0x8000, 0, 3));
clk_dm(IMX8MN_CLK_AHB,
- imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels,
+ imx8m_clk_composite_critical(dev, "ahb", imx8mn_ahb_sels,
base + 0x9000));
clk_dm(IMX8MN_CLK_IPG_ROOT,
imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
clk_dm(IMX8MN_CLK_ENET_AXI,
- imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels,
+ imx8m_clk_composite(dev, "enet_axi", imx8mn_enet_axi_sels,
base + 0x8880));
clk_dm(IMX8MN_CLK_NAND_USDHC_BUS,
- imx8m_clk_composite_critical("nand_usdhc_bus",
+ imx8m_clk_composite_critical(dev, "nand_usdhc_bus",
imx8mn_nand_usdhc_sels,
base + 0x8900));
clk_dm(IMX8MN_CLK_USB_BUS,
- imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
+ imx8m_clk_composite(dev, "usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
/* IP */
clk_dm(IMX8MN_CLK_USDHC1,
- imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels,
+ imx8m_clk_composite(dev, "usdhc1", imx8mn_usdhc1_sels,
base + 0xac00));
clk_dm(IMX8MN_CLK_USDHC2,
- imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
+ imx8m_clk_composite(dev, "usdhc2", imx8mn_usdhc2_sels,
base + 0xac80));
clk_dm(IMX8MN_CLK_I2C1,
- imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
+ imx8m_clk_composite(dev, "i2c1", imx8mn_i2c1_sels, base + 0xad00));
clk_dm(IMX8MN_CLK_I2C2,
- imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
+ imx8m_clk_composite(dev, "i2c2", imx8mn_i2c2_sels, base + 0xad80));
clk_dm(IMX8MN_CLK_I2C3,
- imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
+ imx8m_clk_composite(dev, "i2c3", imx8mn_i2c3_sels, base + 0xae00));
clk_dm(IMX8MN_CLK_I2C4,
- imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
+ imx8m_clk_composite(dev, "i2c4", imx8mn_i2c4_sels, base + 0xae80));
clk_dm(IMX8MN_CLK_UART1,
- imx8m_clk_composite("uart1", imx8mn_uart1_sels, base + 0xaf00));
+ imx8m_clk_composite(dev, "uart1", imx8mn_uart1_sels, base + 0xaf00));
clk_dm(IMX8MN_CLK_UART2,
- imx8m_clk_composite("uart2", imx8mn_uart2_sels, base + 0xaf80));
+ imx8m_clk_composite(dev, "uart2", imx8mn_uart2_sels, base + 0xaf80));
clk_dm(IMX8MN_CLK_UART3,
- imx8m_clk_composite("uart3", imx8mn_uart3_sels, base + 0xb000));
+ imx8m_clk_composite(dev, "uart3", imx8mn_uart3_sels, base + 0xb000));
clk_dm(IMX8MN_CLK_UART4,
- imx8m_clk_composite("uart4", imx8mn_uart4_sels, base + 0xb080));
+ imx8m_clk_composite(dev, "uart4", imx8mn_uart4_sels, base + 0xb080));
clk_dm(IMX8MN_CLK_WDOG,
- imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
+ imx8m_clk_composite(dev, "wdog", imx8mn_wdog_sels, base + 0xb900));
clk_dm(IMX8MN_CLK_USDHC3,
- imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
+ imx8m_clk_composite(dev, "usdhc3", imx8mn_usdhc3_sels,
base + 0xbc80));
clk_dm(IMX8MN_CLK_NAND,
- imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00));
+ imx8m_clk_composite(dev, "nand", imx8mn_nand_sels, base + 0xab00));
clk_dm(IMX8MN_CLK_QSPI,
- imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
+ imx8m_clk_composite(dev, "qspi", imx8mn_qspi_sels, base + 0xab80));
clk_dm(IMX8MN_CLK_USB_CORE_REF,
- imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
+ imx8m_clk_composite(dev, "usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
clk_dm(IMX8MN_CLK_USB_PHY_REF,
- imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
+ imx8m_clk_composite(dev, "usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
clk_dm(IMX8MN_CLK_I2C1_ROOT,
imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0));
/* clks not needed in SPL stage */
#ifndef CONFIG_XPL_BUILD
clk_dm(IMX8MN_CLK_ENET_REF,
- imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
+ imx8m_clk_composite(dev, "enet_ref", imx8mn_enet_ref_sels,
base + 0xa980));
clk_dm(IMX8MN_CLK_ENET_TIMER,
- imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels,
+ imx8m_clk_composite(dev, "enet_timer", imx8mn_enet_timer_sels,
base + 0xaa00));
clk_dm(IMX8MN_CLK_ENET_PHY_REF,
- imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels,
+ imx8m_clk_composite(dev, "enet_phy", imx8mn_enet_phy_sels,
base + 0xaa80));
clk_dm(IMX8MN_CLK_ENET1_ROOT,
imx_clk_gate4(dev, "enet1_root_clk", "enet_axi",
base + 0x40a0, 0));
clk_dm(IMX8MN_CLK_PWM1,
- imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380));
+ imx8m_clk_composite(dev, "pwm1", imx8mn_pwm1_sels, base + 0xb380));
clk_dm(IMX8MN_CLK_PWM2,
- imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400));
+ imx8m_clk_composite(dev, "pwm2", imx8mn_pwm2_sels, base + 0xb400));
clk_dm(IMX8MN_CLK_PWM3,
- imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480));
+ imx8m_clk_composite(dev, "pwm3", imx8mn_pwm3_sels, base + 0xb480));
clk_dm(IMX8MN_CLK_PWM4,
- imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500));
+ imx8m_clk_composite(dev, "pwm4", imx8mn_pwm4_sels, base + 0xb500));
clk_dm(IMX8MN_CLK_PWM1_ROOT,
imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0));
clk_dm(IMX8MN_CLK_PWM2_ROOT,
#if CONFIG_IS_ENABLED(DM_SPI)
clk_dm(IMX8MN_CLK_ECSPI1,
- imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
+ imx8m_clk_composite(dev, "ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
clk_dm(IMX8MN_CLK_ECSPI2,
- imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
+ imx8m_clk_composite(dev, "ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
clk_dm(IMX8MN_CLK_ECSPI3,
- imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
+ imx8m_clk_composite(dev, "ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
clk_dm(IMX8MN_CLK_ECSPI1_ROOT,
imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
clk_dm(IMX8MN_CLK_ECSPI2_ROOT,
clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
- clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite("hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380));
- clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800));
- clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
- clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
- clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical("noc", imx8mp_noc_sels, base + 0x8d00));
- clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical("noc_io", imx8mp_noc_io_sels, base + 0x8d80));
+ clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite(dev, "hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380));
+ clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical(dev, "main_axi", imx8mp_main_axi_sels, base + 0x8800));
+ clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical(dev, "enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
+ clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical(dev, "nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
+ clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical(dev, "noc", imx8mp_noc_sels, base + 0x8d00));
+ clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical(dev, "noc_io", imx8mp_noc_io_sels, base + 0x8d80));
- clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical("ahb_root", imx8mp_ahb_sels, base + 0x9000));
+ clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical(dev, "ahb_root", imx8mp_ahb_sels, base + 0x9000));
clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb_root", base + 0x9080, 0, 1));
- clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000));
- clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
- clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite("pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400));
- clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
- clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
- clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880));
- clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900));
- clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
- clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
- clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
- clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite("qspi", imx8mp_qspi_sels, base + 0xab80));
- clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite("usdhc1", imx8mp_usdhc1_sels, base + 0xac00));
- clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite("usdhc2", imx8mp_usdhc2_sels, base + 0xac80));
- clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite("i2c1", imx8mp_i2c1_sels, base + 0xad00));
- clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite("i2c2", imx8mp_i2c2_sels, base + 0xad80));
- clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite("i2c3", imx8mp_i2c3_sels, base + 0xae00));
- clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mp_i2c4_sels, base + 0xae80));
-
- clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite("uart1", imx8mp_uart1_sels, base + 0xaf00));
- clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2", imx8mp_uart2_sels, base + 0xaf80));
- clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3", imx8mp_uart3_sels, base + 0xb000));
- clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4", imx8mp_uart4_sels, base + 0xb080));
- clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite("usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100));
- clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180));
- clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200));
- clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base + 0xb280));
- clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base + 0xb300));
- clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical("pwm1", imx8mp_pwm1_sels, base + 0xb380));
- clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical("pwm2", imx8mp_pwm2_sels, base + 0xb400));
- clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical("pwm3", imx8mp_pwm3_sels, base + 0xb480));
- clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical("pwm4", imx8mp_pwm4_sels, base + 0xb500));
- clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base + 0xc180));
-
- clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900));
- clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite("usdhc3", imx8mp_usdhc3_sels, base + 0xbc80));
+ clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite(dev, "dram_alt", imx8mp_dram_alt_sels, base + 0xa000));
+ clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical(dev, "dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
+ clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite(dev, "pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400));
+ clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite(dev, "i2c5", imx8mp_i2c5_sels, base + 0xa480));
+ clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite(dev, "i2c6", imx8mp_i2c6_sels, base + 0xa500));
+ clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite(dev, "enet_qos", imx8mp_enet_qos_sels, base + 0xa880));
+ clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite(dev, "enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900));
+ clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite(dev, "enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
+ clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite(dev, "enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
+ clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite(dev, "enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
+ clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite(dev, "qspi", imx8mp_qspi_sels, base + 0xab80));
+ clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite(dev, "usdhc1", imx8mp_usdhc1_sels, base + 0xac00));
+ clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite(dev, "usdhc2", imx8mp_usdhc2_sels, base + 0xac80));
+ clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite(dev, "i2c1", imx8mp_i2c1_sels, base + 0xad00));
+ clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite(dev, "i2c2", imx8mp_i2c2_sels, base + 0xad80));
+ clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite(dev, "i2c3", imx8mp_i2c3_sels, base + 0xae00));
+ clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite(dev, "i2c4", imx8mp_i2c4_sels, base + 0xae80));
+
+ clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite(dev, "uart1", imx8mp_uart1_sels, base + 0xaf00));
+ clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite(dev, "uart2", imx8mp_uart2_sels, base + 0xaf80));
+ clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite(dev, "uart3", imx8mp_uart3_sels, base + 0xb000));
+ clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite(dev, "uart4", imx8mp_uart4_sels, base + 0xb080));
+ clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite(dev, "usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100));
+ clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite(dev, "usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180));
+ clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical(dev, "gic", imx8mp_gic_sels, base + 0xb200));
+ clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite(dev, "ecspi1", imx8mp_ecspi1_sels, base + 0xb280));
+ clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite(dev, "ecspi2", imx8mp_ecspi2_sels, base + 0xb300));
+ clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical(dev, "pwm1", imx8mp_pwm1_sels, base + 0xb380));
+ clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical(dev, "pwm2", imx8mp_pwm2_sels, base + 0xb400));
+ clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical(dev, "pwm3", imx8mp_pwm3_sels, base + 0xb480));
+ clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical(dev, "pwm4", imx8mp_pwm4_sels, base + 0xb500));
+ clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite(dev, "ecspi3", imx8mp_ecspi3_sels, base + 0xc180));
+
+ clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite(dev, "wdog", imx8mp_wdog_sels, base + 0xb900));
+ clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite(dev, "usdhc3", imx8mp_usdhc3_sels, base + 0xbc80));
clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4));
clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags(dev, "dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels)));
clk_dm(IMX8MQ_CLK_AHB,
- imx8m_clk_composite_critical("ahb", imx8mq_ahb_sels,
+ imx8m_clk_composite_critical(dev, "ahb", imx8mq_ahb_sels,
base + 0x9000));
clk_dm(IMX8MQ_CLK_IPG_ROOT,
imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
clk_dm(IMX8MQ_CLK_ENET_AXI,
- imx8m_clk_composite("enet_axi", imx8mq_enet_axi_sels,
+ imx8m_clk_composite(dev, "enet_axi", imx8mq_enet_axi_sels,
base + 0x8880));
clk_dm(IMX8MQ_CLK_NAND_USDHC_BUS,
- imx8m_clk_composite_critical("nand_usdhc_bus",
+ imx8m_clk_composite_critical(dev, "nand_usdhc_bus",
imx8mq_nand_usdhc_sels,
base + 0x8900));
clk_dm(IMX8MQ_CLK_USB_BUS,
- imx8m_clk_composite("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80));
+ imx8m_clk_composite(dev, "usb_bus", imx8mq_usb_bus_sels, base + 0x8b80));
/* DRAM */
clk_dm(IMX8MQ_CLK_DRAM_CORE,
imx_clk_mux2(dev, "dram_core_clk", base + 0x9800, 24, 1,
imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels)));
clk_dm(IMX8MQ_CLK_DRAM_ALT,
- imx8m_clk_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000));
+ imx8m_clk_composite(dev, "dram_alt", imx8mq_dram_alt_sels, base + 0xa000));
clk_dm(IMX8MQ_CLK_DRAM_APB,
- imx8m_clk_composite_critical("dram_apb", imx8mq_dram_apb_sels, base + 0xa080));
+ imx8m_clk_composite_critical(dev, "dram_apb", imx8mq_dram_apb_sels, base + 0xa080));
/* IP */
clk_dm(IMX8MQ_CLK_USDHC1,
- imx8m_clk_composite("usdhc1", imx8mq_usdhc1_sels,
+ imx8m_clk_composite(dev, "usdhc1", imx8mq_usdhc1_sels,
base + 0xac00));
clk_dm(IMX8MQ_CLK_USDHC2,
- imx8m_clk_composite("usdhc2", imx8mq_usdhc2_sels,
+ imx8m_clk_composite(dev, "usdhc2", imx8mq_usdhc2_sels,
base + 0xac80));
clk_dm(IMX8MQ_CLK_I2C1,
- imx8m_clk_composite("i2c1", imx8mq_i2c1_sels, base + 0xad00));
+ imx8m_clk_composite(dev, "i2c1", imx8mq_i2c1_sels, base + 0xad00));
clk_dm(IMX8MQ_CLK_I2C2,
- imx8m_clk_composite("i2c2", imx8mq_i2c2_sels, base + 0xad80));
+ imx8m_clk_composite(dev, "i2c2", imx8mq_i2c2_sels, base + 0xad80));
clk_dm(IMX8MQ_CLK_I2C3,
- imx8m_clk_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00));
+ imx8m_clk_composite(dev, "i2c3", imx8mq_i2c3_sels, base + 0xae00));
clk_dm(IMX8MQ_CLK_I2C4,
- imx8m_clk_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80));
+ imx8m_clk_composite(dev, "i2c4", imx8mq_i2c4_sels, base + 0xae80));
clk_dm(IMX8MQ_CLK_WDOG,
- imx8m_clk_composite("wdog", imx8mq_wdog_sels, base + 0xb900));
+ imx8m_clk_composite(dev, "wdog", imx8mq_wdog_sels, base + 0xb900));
clk_dm(IMX8MQ_CLK_UART1,
- imx8m_clk_composite("uart1", imx8mq_uart1_sels, base + 0xaf00));
+ imx8m_clk_composite(dev, "uart1", imx8mq_uart1_sels, base + 0xaf00));
clk_dm(IMX8MQ_CLK_UART2,
- imx8m_clk_composite("uart2", imx8mq_uart2_sels, base + 0xaf80));
+ imx8m_clk_composite(dev, "uart2", imx8mq_uart2_sels, base + 0xaf80));
clk_dm(IMX8MQ_CLK_UART3,
- imx8m_clk_composite("uart3", imx8mq_uart3_sels, base + 0xb000));
+ imx8m_clk_composite(dev, "uart3", imx8mq_uart3_sels, base + 0xb000));
clk_dm(IMX8MQ_CLK_UART4,
- imx8m_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080));
+ imx8m_clk_composite(dev, "uart4", imx8mq_uart4_sels, base + 0xb080));
clk_dm(IMX8MQ_CLK_QSPI,
- imx8m_clk_composite("qspi", imx8mq_qspi_sels, base + 0xab80));
+ imx8m_clk_composite(dev, "qspi", imx8mq_qspi_sels, base + 0xab80));
clk_dm(IMX8MQ_CLK_USB_CORE_REF,
- imx8m_clk_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100));
+ imx8m_clk_composite(dev, "usb_core_ref", imx8mq_usb_core_sels, base + 0xb100));
clk_dm(IMX8MQ_CLK_USB_PHY_REF,
- imx8m_clk_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180));
+ imx8m_clk_composite(dev, "usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180));
clk_dm(IMX8MQ_CLK_ECSPI1,
- imx8m_clk_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280));
+ imx8m_clk_composite(dev, "ecspi1", imx8mq_ecspi1_sels, base + 0xb280));
clk_dm(IMX8MQ_CLK_ECSPI2,
- imx8m_clk_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300));
+ imx8m_clk_composite(dev, "ecspi2", imx8mq_ecspi2_sels, base + 0xb300));
clk_dm(IMX8MQ_CLK_ECSPI3,
- imx8m_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180));
+ imx8m_clk_composite(dev, "ecspi3", imx8mq_ecspi3_sels, base + 0xc180));
clk_dm(IMX8MQ_CLK_ECSPI1_ROOT,
imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
imx_clk_gate4(dev, "usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0));
clk_dm(IMX8MQ_CLK_ENET_REF,
- imx8m_clk_composite("enet_ref", imx8mq_enet_ref_sels,
+ imx8m_clk_composite(dev, "enet_ref", imx8mq_enet_ref_sels,
base + 0xa980));
clk_dm(IMX8MQ_CLK_ENET_TIMER,
- imx8m_clk_composite("enet_timer", imx8mq_enet_timer_sels,
+ imx8m_clk_composite(dev, "enet_timer", imx8mq_enet_timer_sels,
base + 0xaa00));
clk_dm(IMX8MQ_CLK_ENET_PHY_REF,
- imx8m_clk_composite("enet_phy", imx8mq_enet_phy_sels,
+ imx8m_clk_composite(dev, "enet_phy", imx8mq_enet_phy_sels,
base + 0xaa80));
clk_dm(IMX8MQ_CLK_ENET1_ROOT,
imx_clk_gate4(dev, "enet1_root_clk", "enet_axi",
reg, shift, 0, NULL);
}
-struct clk *imx8m_clk_composite_flags(const char *name,
+struct clk *imx8m_clk_composite_flags(struct udevice *dev, const char *name,
const char * const *parent_names,
int num_parents, void __iomem *reg, unsigned long flags);
-#define __imx8m_clk_composite(name, parent_names, reg, flags) \
- imx8m_clk_composite_flags(name, parent_names, \
+#define __imx8m_clk_composite(dev, name, parent_names, reg, flags) \
+ imx8m_clk_composite_flags(dev, name, parent_names, \
ARRAY_SIZE(parent_names), reg, \
flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
-#define imx8m_clk_composite(name, parent_names, reg) \
- __imx8m_clk_composite(name, parent_names, reg, 0)
+#define imx8m_clk_composite(dev, name, parent_names, reg) \
+ __imx8m_clk_composite(dev, name, parent_names, reg, 0)
-#define imx8m_clk_composite_critical(name, parent_names, reg) \
- __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
+#define imx8m_clk_composite_critical(dev, name, parent_names, reg) \
+ __imx8m_clk_composite(dev, name, parent_names, reg, CLK_IS_CRITICAL)
struct clk *imx93_clk_composite_flags(const char *name,
const char * const *parent_names,
git.openpandora.org / pandora-u-boot.git / commitdiff