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ARM: tegra: Enable PCIe controller on Beaver
authorThierry Reding <thierry.reding@gmail.com>
Fri, 9 Aug 2013 14:49:28 +0000 (16:49 +0200)
committerStephen Warren <swarren@nvidia.com>
Mon, 12 Aug 2013 20:20:22 +0000 (14:20 -0600)
PCIe lane 0 is connected to an onboard Gigabit Ethernet (RTL8168evl) and
lane 4 is routed to the board's miniPCIe slot.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

No differences found
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