ARM: imx6: convert GPC to stacked domains
authorMarc Zyngier <marc.zyngier@arm.com>
Mon, 23 Feb 2015 17:45:18 +0000 (17:45 +0000)
committerShawn Guo <shawn.guo@linaro.org>
Mon, 30 Mar 2015 08:42:15 +0000 (16:42 +0800)
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.

This patch does just this, updating the DT files to actually
reflect what the HW provides.

BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.

Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
arch/arm/boot/dts/imx6qdl.dtsi
arch/arm/boot/dts/imx6sl.dtsi
arch/arm/boot/dts/imx6sx.dtsi
arch/arm/mach-imx/common.h
arch/arm/mach-imx/gpc.c
arch/arm/mach-imx/mach-imx6q.c
arch/arm/mach-imx/mach-imx6sl.c
arch/arm/mach-imx/mach-imx6sx.c
arch/arm/mach-imx/pm-imx6.c

index 1b6f380..da09dc4 100644 (file)
@@ -53,6 +53,7 @@
                interrupt-controller;
                reg = <0x00a01000 0x1000>,
                      <0x00a00100 0x100>;
+               interrupt-parent = <&intc>;
        };
 
        clocks {
@@ -82,7 +83,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "simple-bus";
-               interrupt-parent = <&intc>;
+               interrupt-parent = <&gpc>;
                ranges;
 
                dma_apbh: dma-apbh@00110000 {
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = <0x00a00600 0x20>;
                        interrupts = <1 13 0xf01>;
+                       interrupt-parent = <&intc>;
                        clocks = <&clks IMX6QDL_CLK_TWD>;
                };
 
                        gpc: gpc@020dc000 {
                                compatible = "fsl,imx6q-gpc";
                                reg = <0x020dc000 0x4000>;
+                               interrupt-controller;
+                               #interrupt-cells = <3>;
                                interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
                                             <0 90 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-parent = <&intc>;
                        };
 
                        gpr: iomuxc-gpr@020e0000 {
index 36ab8e0..0d0962b 100644 (file)
@@ -72,6 +72,7 @@
                interrupt-controller;
                reg = <0x00a01000 0x1000>,
                      <0x00a00100 0x100>;
+               interrupt-parent = <&intc>;
        };
 
        clocks {
@@ -95,7 +96,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "simple-bus";
-               interrupt-parent = <&intc>;
+               interrupt-parent = <&gpc>;
                ranges;
 
                ocram: sram@00900000 {
                        gpc: gpc@020dc000 {
                                compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
                                reg = <0x020dc000 0x4000>;
+                               interrupt-controller;
+                               #interrupt-cells = <3>;
                                interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-parent = <&intc>;
                        };
 
                        gpr: iomuxc-gpr@020e0000 {
index 7a24fee..dabaf89 100644 (file)
@@ -88,6 +88,7 @@
                interrupt-controller;
                reg = <0x00a01000 0x1000>,
                      <0x00a00100 0x100>;
+               interrupt-parent = <&intc>;
        };
 
        clocks {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "simple-bus";
-               interrupt-parent = <&intc>;
+               interrupt-parent = <&gpc>;
                ranges;
 
                pmu {
                        gpc: gpc@020dc000 {
                                compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
                                reg = <0x020dc000 0x4000>;
+                               interrupt-controller;
+                               #interrupt-cells = <3>;
                                interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-parent = <&intc>;
                        };
 
                        iomuxc: iomuxc@020e0000 {
index 771ecfe..2fbdc28 100644 (file)
@@ -101,7 +101,6 @@ static inline void imx_scu_map_io(void) {}
 static inline void imx_smp_prepare(void) {}
 #endif
 void imx_src_init(void);
-void imx_gpc_init(void);
 void imx_gpc_pre_suspend(bool arm_power_off);
 void imx_gpc_post_resume(void);
 void imx_gpc_mask_all(void);
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge