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clk: socfpga: Support multiple parents for the pll clocks
authorDinh Nguyen <dinguyen@altera.com>
Wed, 19 Feb 2014 21:11:11 +0000 (15:11 -0600)
committerMike Turquette <mturquette@linaro.org>
Wed, 26 Feb 2014 20:23:40 +0000 (12:23 -0800)
The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk.
Update the clock driver to be able to get the correct parent.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

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