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MIPS: Loongson: update cpu-feature-overrides.h
authorWu Zhangjin <wuzhangjin@gmail.com>
Tue, 13 Apr 2010 05:16:34 +0000 (13:16 +0800)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 21 May 2010 20:31:14 +0000 (21:31 +0100)
Loongson doesn't support MIPSR2, therefore, MIPSR2 vectored interrupts
(cpu_has_vint) and MIPSR2 external interrupt controller mode
(cpu_has_veic) are 0.

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/1112/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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